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added webUI

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ParkerTenBroeck 2026-03-05 11:54:40 -05:00
parent a266096f32
commit 0201990df8
16 changed files with 2590 additions and 341 deletions
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13
rtl/circuit._vhdl
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@ -6,19 +6,18 @@ use ieee.numeric_std.all;
entity circuit is
port (
clk: in std_logic; -- 500 Hz, period 2 ms
key: in std_logic_vector(3 downto 0); -- active low
sw: in std_logic_vector(9 downto 0); -- active high
led: out std_logic_vector(9 downto 0) := (others => '0'); -- active high
hex0: out std_logic_vector(6 downto 0) := (others => '0'); -- active low
hex1: out std_logic_vector(6 downto 0) := (others => '0') -- active low
key: in std_logic_vector(31 downto 0); -- active low
sw: in std_logic_vector(31 downto 0); -- active high
led: out std_logic_vector(31 downto 0) := (others => '0'); -- active high
hex: out std_logic_vector(31 downto 0) := (others => '0') -- active low
);
end circuit;
architecture description of circuit is
signal counter: unsigned(9 downto 0) := "0000000000";
signal counter: unsigned(31 downto 0) := x"00000000";
begin
led <= std_logic_vector(counter(9 downto 0));
led <= std_logic_vector(counter);
process(clk)
begin
counter <= counter+1;