diff --git a/conn/src/lib.rs b/conn/src/lib.rs
index 4798ac8..dad0f83 100644
--- a/conn/src/lib.rs
+++ b/conn/src/lib.rs
@@ -11,7 +11,7 @@ pub struct SimState{
 }
 
 static STATE: SimState = SimState{
-    switch: AtomicU32::new(0),
+    switch: AtomicU32::new(512),
     button: AtomicU32::new(0),
     led: AtomicU32::new(0),
     hex: AtomicU32::new(0),
@@ -52,9 +52,10 @@ pub extern "C" fn ffi_get_key() -> u32 {
 #[no_mangle]
 pub extern "C" fn ffi_set_outputs(led: u32, hex: u32) {
     if STATE.led.swap(led, Ordering::Relaxed) != led{
-        println!("LED={:#x?}", STATE.led.load(Ordering::Relaxed))
+        eprintln!("LED={}", STATE.led.load(Ordering::Relaxed))
     }
     if STATE.hex.swap(hex, Ordering::Relaxed) != hex{
-        println!("HEX={:#x?}", STATE.hex.load(Ordering::Relaxed))
+        eprintln!("HEX={}", STATE.hex.load(Ordering::Relaxed))
     }
+    std::thread::sleep(std::time::Duration::from_millis(1));
 }
\ No newline at end of file
diff --git a/relay/.gitignore b/relay/.gitignore
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+dependencies = [
+ "libc",
+ "windows-sys 0.60.2",
+]
+
+[[package]]
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+source = "registry+https://github.com/rust-lang/crates.io-index"
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+ "proc-macro2",
+ "quote",
+ "unicode-ident",
+]
+
+[[package]]
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+ "thiserror-impl",
+]
+
+[[package]]
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+ "proc-macro2",
+ "quote",
+ "syn",
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+
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+ "bytes",
+ "libc",
+ "mio",
+ "pin-project-lite",
+ "signal-hook-registry",
+ "socket2",
+ "tokio-macros",
+ "windows-sys 0.61.2",
+]
+
+[[package]]
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+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
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+dependencies = [
+ "futures-util",
+ "log",
+ "tokio",
+ "tungstenite",
+]
+
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+ "bytes",
+ "futures-core",
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+ "futures-core",
+ "futures-util",
+ "pin-project-lite",
+ "sync_wrapper",
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+ "tower-service",
+ "tracing",
+]
+
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+ "bitflags",
+ "bytes",
+ "futures-core",
+ "futures-util",
+ "http",
+ "http-body",
+ "http-body-util",
+ "http-range-header",
+ "httpdate",
+ "mime",
+ "mime_guess",
+ "percent-encoding",
+ "pin-project-lite",
+ "tokio",
+ "tokio-util",
+ "tower-layer",
+ "tower-service",
+ "tracing",
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+
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+ "log",
+ "pin-project-lite",
+ "tracing-core",
+]
+
+[[package]]
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+ "once_cell",
+]
+
+[[package]]
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+dependencies = [
+ "bytes",
+ "data-encoding",
+ "http",
+ "httparse",
+ "log",
+ "rand",
+ "sha1",
+ "thiserror",
+ "utf-8",
+]
+
+[[package]]
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+]
+
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+ "windows-targets",
+]
+
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+ "windows-link",
+]
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+dependencies = [
+ "windows-link",
+ "windows_aarch64_gnullvm",
+ "windows_aarch64_msvc",
+ "windows_i686_gnu",
+ "windows_i686_gnullvm",
+ "windows_i686_msvc",
+ "windows_x86_64_gnu",
+ "windows_x86_64_gnullvm",
+ "windows_x86_64_msvc",
+]
+
+[[package]]
+name = "windows_aarch64_gnullvm"
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+
+[[package]]
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+
+[[package]]
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+version = "0.51.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "d7249219f66ced02969388cf2bb044a09756a083d0fab1e566056b04d9fbcaa5"
+
+[[package]]
+name = "zerocopy"
+version = "0.8.40"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "a789c6e490b576db9f7e6b6d661bcc9799f7c0ac8352f56ea20193b2681532e5"
+dependencies = [
+ "zerocopy-derive",
+]
+
+[[package]]
+name = "zerocopy-derive"
+version = "0.8.40"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "f65c489a7071a749c849713807783f70672b28094011623e200cb86dcb835953"
+dependencies = [
+ "proc-macro2",
+ "quote",
+ "syn",
+]
+
+[[package]]
+name = "zmij"
+version = "1.0.21"
+source = "registry+https://github.com/rust-lang/crates.io-index"
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diff --git a/relay/Cargo.toml b/relay/Cargo.toml
new file mode 100644
index 0000000..0e17f78
--- /dev/null
+++ b/relay/Cargo.toml
@@ -0,0 +1,12 @@
+[package]
+name = "relay"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+axum = { version = "0.8", features = ["ws"] }
+tokio = { version = "1", features = ["rt-multi-thread", "macros", "process", "io-util", "sync"] }
+tower-http = { version = "0.6", features = ["fs", "trace"] }
+futures-util = "0.3"
+serde = { version = "1", features = ["derive"] }
+serde_json = "1"
\ No newline at end of file
diff --git a/relay/src/build.rs b/relay/src/build.rs
new file mode 100644
index 0000000..e5298c6
--- /dev/null
+++ b/relay/src/build.rs
@@ -0,0 +1,92 @@
+use std::{collections::HashMap, ops::Deref, path::{Path, PathBuf}};
+use tokio::{
+    process::{Child, Command},
+};
+
+async fn ensure_ok(child: Child) -> Result<(), Box<dyn std::error::Error + Send + Sync>>{
+    let result = child.wait_with_output().await?;
+    if !result.status.success(){
+        return Err(format!("{}\n{}", String::from_utf8_lossy(&result.stdout), String::from_utf8_lossy(&result.stderr)))?
+    }
+    Ok(())
+}
+
+pub struct TempDir(PathBuf);
+impl Drop for TempDir{
+    fn drop(&mut self) {
+        _ = std::fs::remove_dir_all(&self.0)
+    }
+}
+
+impl Deref for TempDir{
+    type Target = PathBuf;
+    
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+
+impl AsRef<PathBuf> for TempDir{
+    fn as_ref(&self) -> &PathBuf {
+        &self.0
+    }
+}
+impl AsRef<Path> for TempDir{
+    fn as_ref(&self) -> &Path {
+        &self.0
+    }
+}
+
+
+pub async fn build(files: HashMap<String, String>) -> Result<TempDir, Box<dyn std::error::Error + Send + Sync>>{
+        use std::hash::*;
+        let mut hasher = std::hash::DefaultHasher::default();
+        for (key, value) in &files{
+            key.hash(&mut hasher);
+            value.hash(&mut hasher);
+        }
+        let hash = hasher.finish();
+
+        let mut work_dir = std::env::temp_dir();
+        work_dir.push(format!("ghdl-relay-{hash:x?}"));
+        _ = std::fs::create_dir(&work_dir);
+        let work_dir = TempDir(work_dir);
+
+
+        for (name, contents) in &files{
+            let mut path = work_dir.clone();
+            path.push(name);
+            std::fs::write(path, contents)?;
+        }
+        
+        
+        let mut cmd = Command::new("ghdl");
+        cmd.kill_on_drop(true);
+        cmd.args(["-a", "-g", "--std=08"]);
+        for name in files.keys(){
+            let mut path = work_dir.clone();
+            path.push(name);
+            cmd.arg(path);
+        }
+        cmd.arg(std::fs::canonicalize("../rtl/tb.vhdl")?);
+        
+        cmd.stdin(std::process::Stdio::piped())
+            .stdout(std::process::Stdio::piped())
+            .stderr(std::process::Stdio::piped());
+        
+        cmd.current_dir(&work_dir);
+        ensure_ok(cmd.spawn()?).await?;
+
+        let mut cmd = Command::new("ghdl");
+        cmd.kill_on_drop(true);
+        cmd.args(["-e", "--std=08"]);
+        cmd.arg(format!("-Wl,{}", std::fs::canonicalize("../conn/target/release/libvhdl_ui.a")?.display()));
+        cmd.arg("tb");
+        cmd.current_dir(&work_dir);
+        cmd.stdin(std::process::Stdio::piped())
+            .stdout(std::process::Stdio::piped())
+            .stderr(std::process::Stdio::piped());
+        ensure_ok(cmd.spawn()?).await?;
+
+        Ok(work_dir)
+}
\ No newline at end of file
diff --git a/relay/src/main.rs b/relay/src/main.rs
new file mode 100644
index 0000000..8824596
--- /dev/null
+++ b/relay/src/main.rs
@@ -0,0 +1,153 @@
+use axum::{
+    Router,
+    extract::ws::{Message, WebSocket, WebSocketUpgrade},
+    routing::get,
+};
+use futures_util::{SinkExt, StreamExt};
+use serde::{Deserialize, Serialize};
+use std::{collections::HashMap, net::SocketAddr};
+use tokio::{
+    io::{AsyncBufReadExt, BufReader},
+};
+use tower_http::services::ServeDir;
+
+pub mod build;
+pub mod run;
+
+
+#[tokio::main]
+async fn main() {
+    let app = Router::new()
+        .route(
+            "/ws",
+            get(|ws: WebSocketUpgrade| async move { ws.on_upgrade(ws_handler) }),
+        )
+        .fallback_service(ServeDir::new("ui"));
+
+    let addr = SocketAddr::from(([127, 0, 0, 1], 8080));
+    println!("Open UI: http://{}/", addr);
+
+    axum::serve(tokio::net::TcpListener::bind(addr).await.unwrap(), app)
+        .await
+        .unwrap();
+}
+
+
+#[derive(Debug, Clone, Serialize, Deserialize)]
+#[serde(tag = "type", rename_all = "snake_case")]
+struct ClientInput{
+    /// bitfield of 32 switches
+    switch: u32, 
+    /// bitfield of 32 buttons
+    buttons: u32
+}
+
+#[derive(Debug, Clone, Serialize, Deserialize)]
+#[serde(rename_all = "snake_case")]
+enum ServerMsg<'a> {
+    Log { stream: &'a str, line: &'a str },
+    /// bitfield of 32 leds
+    Led(u32),
+    /// bitfield of 4 hex displays, 7 segment with decimal
+    Hex(u32)
+}
+
+async fn ws_handler(socket: WebSocket) {
+    let (mut sender, mut receiver) = socket.split();
+
+    let files = if let Some(Ok(Message::Text(msg))) = receiver.next().await
+        && let Ok(files) = serde_json::from_str::<'_, HashMap<String, String>>(&msg)
+    {  
+        files
+    } else {
+        return;
+    };
+
+
+    let artifact_dir = match build::build(files).await{
+        Ok(dir) => dir,
+        Err(err) => {
+            _ = sender.send(Message::Text(format!("Failed to build: {err}").into())).await;
+            return;
+        },
+    };
+
+    let (_process, mut sin, sout, serr) = match run::run(&artifact_dir).await{
+        Ok(process) => process,
+        Err(err) => {
+            _ = sender.send(Message::Text(format!("Failed to run: {err}").into())).await;
+            return;
+        },
+    };
+    let mut sout = BufReader::new(sout).lines();
+    let mut serr = BufReader::new(serr).lines();
+
+    let artifact_prefix = artifact_dir.to_str().unwrap_or("\0\0NOPE");
+    
+    let result: Result<(), Box<dyn std::error::Error + Sync + Send>> = async {
+        loop{
+            tokio::select! {
+                receive = receiver.next() => {
+                    match receive{
+                        Some(Ok(Message::Close(_))) => break,
+                        Some(Ok(Message::Text(msg))) => {
+                            let input = serde_json::from_str::<'_, ClientInput>(&msg)?;
+                            use tokio::io::AsyncWriteExt;
+                            sin.write_all(format!("key={}\n", input.buttons).as_bytes()).await?;
+                            sin.write_all(format!("sw={}\n", input.switch).as_bytes()).await?;
+                        },
+                        Some(Ok(_)) => {},
+                        Some(Err(err)) => Err(err)?,
+                        _ => break,
+                    }
+
+                }
+                out = sout.next_line() => {
+                    match out{
+                        Ok(Some(line)) => {
+                            
+                            let msg = ServerMsg::Log {
+                                stream: "stdout",
+                                line: line.strip_prefix(artifact_prefix).unwrap_or(&line),
+                            };
+                            sender.send(Message::Text(serde_json::to_string(&msg)?.into())).await?;
+                        },
+                        Ok(None) => break,
+                        Err(err) => {
+                            Err(format!("Failed to read proccess sout: {err}"))?;
+                        }
+                    }
+                }
+                err = serr.next_line() => {
+                    match err{
+                        Ok(Some(line)) => {
+                            let msg = if let Some(repr) = line.strip_prefix("LED="){
+                                ServerMsg::Led(repr.parse().unwrap_or(0))
+                            }else if let Some(repr) = line.strip_prefix("HEX="){
+                                ServerMsg::Hex(repr.parse().unwrap_or(0))
+                            }else{
+                                ServerMsg::Log {
+                                    stream: "stderr",
+                                    line: line.strip_prefix(artifact_prefix).unwrap_or(&line),
+                                }
+                            };
+                            sender.send(Message::Text(serde_json::to_string(&msg)?.into())).await?;
+                        },
+                        Ok(None) => break,
+                        Err(err) => {
+                            Err(format!("Failed to read proccess serr: {err}"))?
+                        }
+                    }
+                }
+            }        
+        }
+        Ok(())
+    }.await;
+
+    match result{
+        Ok(_) => {},
+        Err(err) => {
+            _ = sender.send(Message::Text(format!("{err}").into())).await;
+        },
+    }
+}
\ No newline at end of file
diff --git a/relay/src/run.rs b/relay/src/run.rs
new file mode 100644
index 0000000..a2eed37
--- /dev/null
+++ b/relay/src/run.rs
@@ -0,0 +1,31 @@
+use std::{path::Path};
+
+use tokio::process::{Child, ChildStdin, ChildStdout, ChildStderr, Command};
+
+pub struct Process{
+    child: Child,
+}
+
+impl Drop for Process{
+    fn drop(&mut self) {
+        _ = self.child.start_kill()
+    }
+}
+
+pub async fn run(artifact_dir: &Path)  -> Result<(Process, ChildStdin, ChildStdout, ChildStderr), Box<dyn std::error::Error + Send + Sync>>{
+        let mut cmd = Command::new("ghdl");
+    cmd.args(["-r", "--std=08", "tb", "--stop-delta=2147483647", "--unbuffered"]);
+    cmd.current_dir(artifact_dir);
+
+    cmd.stdin(std::process::Stdio::piped())
+        .stdout(std::process::Stdio::piped())
+        .stderr(std::process::Stdio::piped());
+
+    let mut child = cmd.spawn()?;
+
+    let stdin = child.stdin.take().ok_or("no stdin")?;
+    let stdout = child.stdout.take().ok_or("no stdout")?;
+    let stderr = child.stderr.take().ok_or("no stderr")?;
+
+    Ok((Process { child }, stdin, stdout, stderr))
+}
\ No newline at end of file
diff --git a/relay/ui/app.js b/relay/ui/app.js
new file mode 100644
index 0000000..dd0907f
--- /dev/null
+++ b/relay/ui/app.js
@@ -0,0 +1,468 @@
+// ----- LocalStorage keys -----
+const LS_KEY_VHDL = "circuit_ui:circuit.vhdl";
+
+// ----- State -----
+let ws = null;
+let isConnected = false;
+
+let switches = 0 >>> 0; // u32
+let buttons  = 0 >>> 0; // u32
+
+let autoscroll = true;
+
+// ----- DOM -----
+const wsPill = document.getElementById("wsPill");
+const wsUrlText = document.getElementById("wsUrlText");
+
+const connectToggleBtn = document.getElementById("connectToggleBtn");
+const sendInputsBtn = document.getElementById("sendInputsBtn");
+
+const vhdlEditor = document.getElementById("vhdlEditor");
+const lineGutter = document.getElementById("lineGutter");
+const loadExampleBtn = document.getElementById("loadExampleBtn");
+
+const ledRow = document.getElementById("ledRow");
+const ledLabels = document.getElementById("ledLabels");
+const hexRow = document.getElementById("hexRow");
+
+const switchGrid = document.getElementById("switchGrid");
+const buttonGrid = document.getElementById("buttonGrid");
+
+const logView = document.getElementById("logView");
+const clearLogBtn = document.getElementById("clearLogBtn");
+const autoscrollBtn = document.getElementById("autoscrollBtn");
+
+const allSwOffBtn = document.getElementById("allSwOffBtn");
+const allSwOnBtn = document.getElementById("allSwOnBtn");
+
+// ----- Helpers -----
+function wsUrl() {
+  const proto = (location.protocol === "https:") ? "wss" : "ws";
+  return `${proto}://${location.host}/ws`;
+}
+
+function setStatus(connected) {
+  isConnected = connected;
+  wsPill.textContent = connected ? "CONNECTED" : "DISCONNECTED";
+  wsPill.style.borderColor = connected ? "rgba(34,197,94,.6)" : "rgba(239,68,68,.6)";
+  wsPill.style.background = connected ? "rgba(34,197,94,.14)" : "rgba(239,68,68,.10)";
+
+  sendInputsBtn.disabled = !connected;
+
+  // single button label
+  connectToggleBtn.textContent = connected ? "Disconnect" : "Connect";
+  connectToggleBtn.classList.toggle("secondary", connected);
+}
+
+function appendLog(stream, line) {
+  const prefix = stream === "stderr" ? "[stderr]" : "[stdout]";
+  logView.textContent += `${prefix} ${line}\n`;
+  if (autoscroll) {
+    logView.scrollTop = logView.scrollHeight;
+  }
+}
+
+function clearLogs() {
+  logView.textContent = "";
+}
+
+function resetOutputsVisuals() {
+  // reset LED/HEX visuals to 0 immediately
+  setLeds(0);
+  setHex(0);
+}
+
+function u32BitGet(x, i) {
+  return ((x >>> i) & 1) === 1;
+}
+
+function u32BitSet(x, i, on) {
+  if (on) return (x | (1 << i)) >>> 0;
+  return (x & ~(1 << i)) >>> 0;
+}
+
+function sendClientInput() {
+  if (!ws || ws.readyState !== WebSocket.OPEN) return;
+
+  const msg = {
+    type: "client_input",
+    switch: switches >>> 0,
+    buttons: buttons >>> 0,
+  };
+  ws.send(JSON.stringify(msg));
+}
+
+function parseHexDigits(hexU32) {
+  const d0 = (hexU32 >>> 0) & 0xFF;
+  const d1 = (hexU32 >>> 8) & 0xFF;
+  const d2 = (hexU32 >>> 16) & 0xFF;
+  const d3 = (hexU32 >>> 24) & 0xFF;
+  return [d0, d1, d2, d3];
+}
+
+// ----- Line numbers -----
+function updateLineNumbers() {
+  const text = vhdlEditor.value || "";
+  // count lines: number of '\n' + 1 (even empty text -> 1 line)
+  const lines = text.length ? (text.split("\n").length) : 1;
+
+  // Build as one string for performance
+  let out = "";
+  for (let i = 1; i <= lines; i++) out += i + "\n";
+  lineGutter.textContent = out;
+
+  syncGutterScroll();
+}
+
+function syncGutterScroll() {
+  // keep gutter aligned to editor scroll
+  lineGutter.scrollTop = vhdlEditor.scrollTop;
+}
+
+// ----- LocalStorage save (debounced) -----
+let saveTimer = null;
+function saveEditorToLocalStorageDebounced() {
+  if (saveTimer) clearTimeout(saveTimer);
+  saveTimer = setTimeout(() => {
+    try {
+      localStorage.setItem(LS_KEY_VHDL, vhdlEditor.value ?? "");
+    } catch (e) {
+      // ignore storage failures (private mode, quota)
+    }
+  }, 250);
+}
+
+function loadEditorFromLocalStorage() {
+  try {
+    const saved = localStorage.getItem(LS_KEY_VHDL);
+    if (saved !== null) return saved;
+  } catch {}
+  return null;
+}
+
+// ----- UI Builders -----
+function buildLeds() {
+  ledRow.innerHTML = "";
+  ledLabels.innerHTML = "";
+
+  for (let i = 0; i < 32; i++) {
+    const el = document.createElement("div");
+    el.className = "led";
+    el.title = `LED[${i}]`;
+    el.dataset.bit = String(i);
+    ledRow.appendChild(el);
+
+    const lab = document.createElement("span");
+    lab.textContent = String(i);
+    ledLabels.appendChild(lab);
+  }
+}
+
+function setLeds(bitsU32) {
+  for (const el of ledRow.children) {
+    const i = Number(el.dataset.bit);
+    el.classList.toggle("on", u32BitGet(bitsU32 >>> 0, i));
+  }
+}
+
+function makeSevenSeg(digitIndex) {
+  const wrap = document.createElement("div");
+
+  const disp = document.createElement("div");
+  disp.className = "sevenSeg";
+  disp.dataset.digit = String(digitIndex);
+
+  const segs = ["a","b","c","d","e","f","g","dp"];
+  for (const s of segs) {
+    const seg = document.createElement("div");
+    seg.className = `seg ${s}`;
+    seg.dataset.seg = s;
+    disp.appendChild(seg);
+  }
+
+  const label = document.createElement("div");
+  label.className = "digitLabel";
+  label.textContent = `HEX[${digitIndex}]`;
+
+  wrap.appendChild(disp);
+  wrap.appendChild(label);
+  return wrap;
+}
+
+function buildHex() {
+  hexRow.innerHTML = "";
+  for (let i = 0; i < 4; i++) {
+    hexRow.appendChild(makeSevenSeg(i));
+  }
+}
+
+function setHex(hexU32) {
+  const digits = parseHexDigits(hexU32 >>> 0);
+
+  for (let i = 0; i < 4; i++) {
+    const byte = digits[i] & 0xFF;
+    const disp = hexRow.querySelector(`.sevenSeg[data-digit="${i}"]`);
+    if (!disp) continue;
+
+    const map = { a:0, b:1, c:2, d:3, e:4, f:5, g:6, dp:7 };
+
+    for (const segEl of disp.querySelectorAll(".seg")) {
+      const name = segEl.dataset.seg;
+      const bit = map[name];
+      const on = ((byte >>> bit) & 1) === 1;
+      segEl.classList.toggle("on", on);
+    }
+  }
+}
+
+function buildSwitches() {
+  switchGrid.innerHTML = "";
+  for (let i = 0; i < 32; i++) {
+    const cell = document.createElement("div");
+    cell.className = "ioCell";
+
+    const label = document.createElement("label");
+    label.textContent = `SW[${i}]`;
+
+    const toggle = document.createElement("div");
+    toggle.className = "toggle";
+    toggle.dataset.bit = String(i);
+    toggle.title = `Toggle switch ${i}`;
+
+    toggle.addEventListener("click", () => {
+      const bit = Number(toggle.dataset.bit);
+      const now = !u32BitGet(switches, bit);
+      switches = u32BitSet(switches, bit, now);
+      toggle.classList.toggle("on", now);
+      sendClientInput();
+    });
+
+    cell.appendChild(toggle);
+    cell.appendChild(label);
+    switchGrid.appendChild(cell);
+  }
+}
+
+function syncSwitchesUI() {
+  for (const toggle of switchGrid.querySelectorAll(".toggle")) {
+    const i = Number(toggle.dataset.bit);
+    toggle.classList.toggle("on", u32BitGet(switches, i));
+  }
+}
+
+function buildButtons() {
+  buttonGrid.innerHTML = "";
+  for (let i = 0; i < 32; i++) {
+    const cell = document.createElement("div");
+    cell.className = "ioCell";
+
+    const label = document.createElement("label");
+    label.textContent = `KEY[${i}]`;
+
+    const btn = document.createElement("button");
+    btn.className = "momentary";
+    btn.type = "button";
+    btn.textContent = "press";
+    btn.dataset.bit = String(i);
+    btn.title = `Momentary button ${i}`;
+
+    const press = () => {
+      const bit = Number(btn.dataset.bit);
+      buttons = u32BitSet(buttons, bit, true);
+      btn.classList.add("down");
+      sendClientInput();
+    };
+
+    const release = () => {
+      const bit = Number(btn.dataset.bit);
+      buttons = u32BitSet(buttons, bit, false);
+      btn.classList.remove("down");
+      sendClientInput();
+    };
+
+    // Mouse
+    btn.addEventListener("mousedown", (e) => { e.preventDefault(); press(); });
+    btn.addEventListener("mouseup",   (e) => { e.preventDefault(); release(); });
+    btn.addEventListener("mouseleave",(e) => { e.preventDefault(); release(); });
+
+    // Touch
+    btn.addEventListener("touchstart",(e) => { e.preventDefault(); press(); }, {passive:false});
+    btn.addEventListener("touchend",  (e) => { e.preventDefault(); release(); }, {passive:false});
+    btn.addEventListener("touchcancel",(e)=> { e.preventDefault(); release(); }, {passive:false});
+
+    cell.appendChild(btn);
+    cell.appendChild(label);
+    buttonGrid.appendChild(cell);
+  }
+}
+
+// ----- WebSocket -----
+function connect() {
+  if (ws && (ws.readyState === WebSocket.OPEN || ws.readyState === WebSocket.CONNECTING)) return;
+
+  // Requirement (3): reset logs + outputs when connect is pressed
+  clearLogs();
+  resetOutputsVisuals();
+
+  const url = wsUrl();
+  wsUrlText.textContent = url;
+
+  ws = new WebSocket(url);
+
+  ws.addEventListener("open", () => {
+    setStatus(true);
+    appendLog("stdout", "WebSocket connected.");
+
+    // First message MUST be the file map
+    const files = {
+      "circuit.vhdl": vhdlEditor.value ?? ""
+    };
+    ws.send(JSON.stringify(files));
+
+    // Push initial input state
+    sendClientInput();
+  });
+
+  ws.addEventListener("message", (ev) => {
+    let parsed = null;
+    try {
+      parsed = JSON.parse(ev.data);
+    } catch {
+      appendLog("stderr", String(ev.data));
+      return;
+    }
+
+
+    if (parsed.log !== undefined) {
+      appendLog(parsed.log.stream ?? "stdout", parsed.log.line ?? "");
+      return;
+    }
+
+    if (parsed.led !== undefined) {
+      const v = (parsed.led ?? parsed.value ?? parsed[0] ?? parsed["0"] ?? 0) >>> 0;
+      setLeds(v);
+      return;
+    }
+
+    if (parsed.hex !== undefined) {
+      const v = (parsed.hex ?? parsed.value ?? parsed[0] ?? parsed["0"] ?? 0) >>> 0;
+      setHex(v);
+      return;
+    }
+
+    appendLog("stderr", `Unknown msg: ${ev.data}`);
+  });
+
+  ws.addEventListener("close", () => {
+    appendLog("stderr", "WebSocket closed.");
+    setStatus(false);
+  });
+
+  ws.addEventListener("error", () => {
+    appendLog("stderr", "WebSocket error.");
+    setStatus(false);
+  });
+}
+
+function disconnect() {
+  if (ws) ws.close();
+}
+
+function toggleConnect() {
+  if (isConnected) disconnect();
+  else connect();
+}
+
+// ----- Wire up controls -----
+connectToggleBtn.addEventListener("click", toggleConnect);
+
+sendInputsBtn.addEventListener("click", () => {
+  appendLog("stdout", `Manual send: sw=${switches >>> 0} key=${buttons >>> 0}`);
+  sendClientInput();
+});
+
+clearLogBtn.addEventListener("click", () => { clearLogs(); });
+
+autoscrollBtn.addEventListener("click", () => {
+  autoscroll = !autoscroll;
+  autoscrollBtn.textContent = `Autoscroll: ${autoscroll ? "on" : "off"}`;
+});
+
+allSwOffBtn.addEventListener("click", () => {
+  switches = 0 >>> 0;
+  syncSwitchesUI();
+  sendClientInput();
+});
+
+allSwOnBtn.addEventListener("click", () => {
+  switches = 0xFFFF_FFFF >>> 0;
+  syncSwitchesUI();
+  sendClientInput();
+});
+
+loadExampleBtn.addEventListener("click", () => {
+  vhdlEditor.value =
+`library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Do not modify the following entity block
+entity circuit is
+port (
+  clk: in std_logic; -- 500 Hz, period 2 ms
+  key: in std_logic_vector(31 downto 0);   -- active low
+  sw: in std_logic_vector(31 downto 0);   -- active high
+  led: out std_logic_vector(31 downto 0) := (others => '0');  -- active high
+  hex: out std_logic_vector(31 downto 0) := (others => '0')  -- active low
+  );
+end circuit;
+
+
+architecture description of circuit is
+  signal counter: unsigned(31 downto 0) := x"00000000";
+begin
+  led <= std_logic_vector(counter);
+  process(clk)
+  begin
+    counter <= counter+1;
+  end process;
+end description;`;
+
+  saveEditorToLocalStorageDebounced();
+  updateLineNumbers();
+});
+
+// Editor events: save + line numbers + gutter sync
+vhdlEditor.addEventListener("input", () => {
+  saveEditorToLocalStorageDebounced();
+  updateLineNumbers();
+});
+
+vhdlEditor.addEventListener("scroll", () => {
+  syncGutterScroll();
+});
+
+// ----- Init -----
+(function init() {
+  wsUrlText.textContent = wsUrl();
+
+  buildLeds();
+  buildHex();
+  buildSwitches();
+  buildButtons();
+
+  resetOutputsVisuals();
+  setStatus(false);
+
+  // Load from localStorage if present
+  const saved = loadEditorFromLocalStorage();
+  if (saved !== null) {
+    vhdlEditor.value = saved;
+  } else {
+    vhdlEditor.value =
+`-- circuit.vhdl
+-- Paste your circuit here. The UI will send it on Connect.`;
+  }
+
+  updateLineNumbers();
+})();
\ No newline at end of file
diff --git a/relay/ui/index.html b/relay/ui/index.html
new file mode 100644
index 0000000..4556b5c
--- /dev/null
+++ b/relay/ui/index.html
@@ -0,0 +1,119 @@
+<!doctype html>
+<html lang="en">
+<head>
+  <meta charset="utf-8" />
+  <meta name="viewport" content="width=device-width,initial-scale=1" />
+  <title>VHDL Circuit UI</title>
+  <link rel="stylesheet" href="styles.css" />
+</head>
+<body>
+  <header class="topbar">
+    <div class="brand">
+      <div class="dot"></div>
+      <div>
+        <div class="title">Circuit Web UI</div>
+        <div class="subtitle">LEDs • HEX • Switches • Buttons • circuit.vhdl</div>
+      </div>
+    </div>
+
+    <div class="controls">
+      <div class="status">
+        <span class="pill" id="wsPill">DISCONNECTED</span>
+        <span class="muted" id="wsUrlText"></span>
+      </div>
+
+      <!-- single toggle button now -->
+      <button id="connectToggleBtn">Connect</button>
+
+      <button id="sendInputsBtn" class="secondary" disabled>Send Inputs</button>
+    </div>
+  </header>
+
+  <main class="grid">
+    <!-- Left: Editor -->
+    <section class="card editor">
+      <div class="cardHeader">
+        <div class="cardTitle">circuit.vhdl</div>
+        <div class="cardActions">
+          <button id="loadExampleBtn" class="secondary">Load example</button>
+        </div>
+      </div>
+
+      <!-- NEW: editor with line-number gutter -->
+      <div class="editorWrap">
+        <pre id="lineGutter" class="lineGutter" aria-hidden="true"></pre>
+        <textarea id="vhdlEditor" spellcheck="false"></textarea>
+      </div>
+
+      <div class="hint">
+        Saved locally as you type. On <b>Connect</b>, the UI sends <code>{"circuit.vhdl": "..."}</code> as the first WebSocket message.
+      </div>
+    </section>
+
+    <!-- Right: IO -->
+    <section class="card io">
+      <div class="cardHeader">
+        <div class="cardTitle">Outputs</div>
+      </div>
+
+      <div class="outputs">
+        <div class="block">
+          <div class="blockTitle">LEDs (32)</div>
+          <div id="ledRow" class="ledRow"></div>
+          <div class="bitLabelRow" id="ledLabels"></div>
+        </div>
+
+        <div class="block">
+          <div class="blockTitle">HEX (4 digits, 7-seg + dp)</div>
+          <div id="hexRow" class="hexRow"></div>
+          <div class="hint small">
+            Assumes each digit is 8 bits: <code>bit0=a</code>, <code>1=b</code>, <code>2=c</code>, <code>3=d</code>, <code>4=e</code>, <code>5=f</code>, <code>6=g</code>, <code>7=dp</code>.
+          </div>
+        </div>
+      </div>
+    </section>
+
+    <!-- Bottom-left: Inputs -->
+    <section class="card inputs">
+      <div class="cardHeader">
+        <div class="cardTitle">Inputs</div>
+        <div class="cardActions">
+          <button id="allSwOffBtn" class="secondary">All switches off</button>
+          <button id="allSwOnBtn" class="secondary">All switches on</button>
+        </div>
+      </div>
+
+      <div class="twoCols">
+        <div class="block">
+          <div class="blockTitle">Switches (32, latched)</div>
+          <div id="switchGrid" class="ioGrid"></div>
+        </div>
+
+        <div class="block">
+          <div class="blockTitle">Buttons (32, momentary)</div>
+          <div id="buttonGrid" class="ioGrid"></div>
+        </div>
+      </div>
+
+      <div class="hint">
+        Switches toggle a bit. Buttons set the bit while pressed (mouse/touch) and clear on release.
+      </div>
+    </section>
+
+    <!-- Bottom-right: Logs -->
+    <section class="card logs">
+      <div class="cardHeader">
+        <div class="cardTitle">Logs</div>
+        <div class="cardActions">
+          <button id="clearLogBtn" class="secondary">Clear</button>
+          <button id="autoscrollBtn" class="secondary">Autoscroll: on</button>
+        </div>
+      </div>
+
+      <pre id="logView" class="logView"></pre>
+    </section>
+  </main>
+
+  <script src="app.js"></script>
+</body>
+</html>
\ No newline at end of file
diff --git a/relay/ui/styles.css b/relay/ui/styles.css
new file mode 100644
index 0000000..830bf2c
--- /dev/null
+++ b/relay/ui/styles.css
@@ -0,0 +1,396 @@
+:root{
+  --bg: #0b0f17;
+  --card: #121a2a;
+  --card2:#0f1726;
+  --text: #e6eefc;
+  --muted:#9fb0d0;
+  --accent:#58a6ff;
+  --ok:#22c55e;
+  --bad:#ef4444;
+  --warn:#f59e0b;
+  --line:#1f2a44;
+  --shadow: 0 12px 30px rgba(0,0,0,.35);
+  --radius: 14px;
+  --mono: ui-monospace, SFMono-Regular, Menlo, Monaco, Consolas, "Liberation Mono", "Courier New", monospace;
+  --sans: ui-sans-serif, system-ui, -apple-system, Segoe UI, Roboto, Helvetica, Arial, "Apple Color Emoji","Segoe UI Emoji";
+}
+
+*{ box-sizing:border-box; }
+html,body{ height:100%; }
+body{
+  margin:0;
+  background: radial-gradient(1000px 600px at 20% -10%, rgba(88,166,255,.20), transparent 60%),
+              radial-gradient(900px 500px at 90% 0%, rgba(34,197,94,.12), transparent 60%),
+              var(--bg);
+  color:var(--text);
+  font-family: var(--sans);
+}
+
+.topbar{
+  position: sticky;
+  top:0;
+  z-index: 10;
+  display:flex;
+  justify-content:space-between;
+  align-items:center;
+  padding:14px 16px;
+  border-bottom:1px solid rgba(255,255,255,.06);
+  background: rgba(11,15,23,.8);
+  backdrop-filter: blur(10px);
+}
+
+.brand{
+  display:flex;
+  gap:12px;
+  align-items:center;
+}
+.brand .dot{
+  width:12px;height:12px;border-radius:50%;
+  background: var(--accent);
+  box-shadow: 0 0 18px rgba(88,166,255,.7);
+}
+.title{ font-weight:700; letter-spacing:.2px; }
+.subtitle{ font-size:12px; color:var(--muted); margin-top:2px; }
+
+.controls{
+  display:flex;
+  gap:10px;
+  align-items:center;
+}
+.status{
+  display:flex;
+  gap:8px;
+  align-items:center;
+  margin-right:6px;
+}
+.pill{
+  font-size:12px;
+  padding:6px 10px;
+  border-radius:999px;
+  border:1px solid rgba(255,255,255,.12);
+  background: rgba(255,255,255,.04);
+}
+.muted{ color:var(--muted); font-size:12px; }
+
+button{
+  border:1px solid rgba(255,255,255,.14);
+  background: rgba(88,166,255,.14);
+  color:var(--text);
+  padding:8px 12px;
+  border-radius:10px;
+  cursor:pointer;
+  transition: transform .05s ease, background .2s ease;
+}
+button:hover{ background: rgba(88,166,255,.20); }
+button:active{ transform: translateY(1px); }
+button.secondary{
+  background: rgba(255,255,255,.06);
+}
+button.secondary:hover{ background: rgba(255,255,255,.10); }
+button:disabled{
+  opacity:.55;
+  cursor:not-allowed;
+}
+
+.grid{
+  display:grid;
+  grid-template-columns: 1.2fr 1fr;
+  grid-template-rows: 420px 1fr;
+  gap:14px;
+  padding:14px;
+}
+
+.card{
+  background: linear-gradient(180deg, rgba(255,255,255,.05), rgba(255,255,255,.03));
+  border:1px solid rgba(255,255,255,.08);
+  border-radius: var(--radius);
+  box-shadow: var(--shadow);
+  overflow:hidden;
+  min-height: 0;
+}
+
+.cardHeader{
+  display:flex;
+  justify-content:space-between;
+  align-items:center;
+  padding:12px 12px;
+  border-bottom:1px solid rgba(255,255,255,.06);
+  background: rgba(0,0,0,.15);
+}
+.cardTitle{ font-weight:700; }
+.cardActions{ display:flex; gap:8px; }
+
+.editor{
+  display:flex;
+  flex-direction:column;
+}
+textarea{
+  width:100%;
+  height:100%;
+  padding:12px;
+  background: rgba(0,0,0,.22);
+  color:var(--text);
+  border:0;
+  outline:none;
+  resize:none;
+  font-family: var(--mono);
+  font-size: 13px;
+  line-height: 1.35;
+}
+.hint{
+  padding:10px 12px;
+  border-top:1px solid rgba(255,255,255,.06);
+  color:var(--muted);
+  font-size:12px;
+  background: rgba(0,0,0,.12);
+}
+.hint.small{ font-size:11px; }
+
+.io .outputs{
+  padding:12px;
+  display:flex;
+  flex-direction:column;
+  gap:14px;
+}
+.blockTitle{
+  font-size:12px;
+  color:var(--muted);
+  margin-bottom:8px;
+}
+
+.ledRow{
+  display:grid;
+  grid-template-columns: repeat(16, 1fr);
+  gap:6px;
+}
+.led{
+  width: 100%;
+  aspect-ratio: 1/1;
+  border-radius: 999px;
+  border:1px solid rgba(255,255,255,.14);
+  background: rgba(255,255,255,.08);
+  box-shadow: inset 0 0 0 2px rgba(0,0,0,.18);
+}
+.led.on{
+  background: rgba(34,197,94,.70);
+  border-color: rgba(34,197,94,.9);
+  box-shadow: 0 0 14px rgba(34,197,94,.45);
+}
+.bitLabelRow{
+  display:grid;
+  grid-template-columns: repeat(16, 1fr);
+  gap:6px;
+  margin-top:6px;
+  color: var(--muted);
+  font-size: 10px;
+  font-family: var(--mono);
+  opacity: .85;
+}
+.bitLabelRow span{
+  text-align:center;
+}
+
+.hexRow{
+  display:flex;
+  gap:14px;
+  flex-wrap:wrap;
+  align-items:center;
+}
+
+/* 7-seg display */
+.sevenSeg{
+  width: 90px;
+  height: 140px;
+  position: relative;
+  background: rgba(0,0,0,.18);
+  border:1px solid rgba(255,255,255,.10);
+  border-radius: 14px;
+  padding:10px;
+}
+.seg{
+  position:absolute;
+  background: rgba(255,255,255,.10);
+  border-radius: 8px;
+  filter: drop-shadow(0 0 0 rgba(0,0,0,0));
+}
+.seg.on{
+  background: rgba(88,166,255,.75);
+  filter: drop-shadow(0 0 8px rgba(88,166,255,.35));
+}
+
+/* segment positions */
+.seg.a{ top:10px; left:18px; width:54px; height:12px; }
+.seg.d{ bottom:10px; left:18px; width:54px; height:12px; }
+.seg.g{ top:64px; left:18px; width:54px; height:12px; }
+
+.seg.f{ top:18px; left:10px; width:12px; height:54px; }
+.seg.b{ top:18px; right:10px; width:12px; height:54px; }
+
+.seg.e{ bottom:18px; left:10px; width:12px; height:54px; }
+.seg.c{ bottom:18px; right:10px; width:12px; height:54px; }
+
+.seg.dp{
+  width:12px; height:12px;
+  bottom:10px; right:10px;
+  border-radius: 999px;
+}
+
+.digitLabel{
+  margin-top:8px;
+  font-family: var(--mono);
+  font-size: 11px;
+  color: var(--muted);
+  text-align:center;
+}
+
+.inputs{
+  grid-column: 1 / 2;
+  display:flex;
+  flex-direction:column;
+  min-height: 0;
+}
+.twoCols{
+  padding:12px;
+  display:grid;
+  grid-template-columns: 1fr 1fr;
+  gap:12px;
+  min-height: 0;
+}
+.ioGrid{
+  display:grid;
+  grid-template-columns: repeat(8, 1fr);
+  gap:8px;
+}
+.ioCell{
+  display:flex;
+  flex-direction:column;
+  gap:6px;
+  align-items:center;
+  padding:8px 6px;
+  background: rgba(0,0,0,.16);
+  border:1px solid rgba(255,255,255,.08);
+  border-radius:12px;
+}
+.ioCell label{
+  font-family: var(--mono);
+  font-size: 11px;
+  color: var(--muted);
+}
+
+.toggle{
+  width: 38px;
+  height: 22px;
+  border-radius: 999px;
+  position: relative;
+  background: rgba(255,255,255,.10);
+  border:1px solid rgba(255,255,255,.14);
+  cursor:pointer;
+}
+.toggle::after{
+  content:"";
+  width: 16px;
+  height: 16px;
+  position:absolute;
+  top:2px;
+  left:2px;
+  border-radius: 999px;
+  background: rgba(255,255,255,.45);
+  transition: left .12s ease, background .12s ease;
+}
+.toggle.on{
+  background: rgba(34,197,94,.24);
+  border-color: rgba(34,197,94,.55);
+}
+.toggle.on::after{
+  left: 20px;
+  background: rgba(34,197,94,.75);
+}
+
+.momentary{
+  width: 40px;
+  height: 28px;
+  border-radius: 10px;
+  border:1px solid rgba(255,255,255,.14);
+  background: rgba(255,255,255,.08);
+  cursor:pointer;
+}
+.momentary.down{
+  background: rgba(245,158,11,.25);
+  border-color: rgba(245,158,11,.55);
+  box-shadow: 0 0 12px rgba(245,158,11,.18);
+}
+
+.logs{
+  grid-column: 2 / 3;
+  display:flex;
+  flex-direction:column;
+  min-height: 0;
+}
+.logView{
+  margin:0;
+  padding:12px;
+  height:100%;
+  overflow:auto;
+  background: rgba(0,0,0,.22);
+  font-family: var(--mono);
+  font-size: 12px;
+  line-height: 1.35;
+  white-space: pre-wrap;
+  word-break: break-word;
+}
+
+/* Responsive */
+@media (max-width: 1100px){
+  .grid{
+    grid-template-columns: 1fr;
+    grid-template-rows: auto;
+  }
+  .inputs, .logs{
+    grid-column: auto;
+  }
+  .twoCols{
+    grid-template-columns: 1fr;
+  }
+}
+
+/* Editor w/ line numbers */
+.editorWrap{
+  display:flex;
+  width:100%;
+  height:100%;
+  min-height: 0;
+  background: rgba(0,0,0,.22);
+}
+
+.lineGutter{
+  margin:0;
+  padding:12px 10px 12px 12px;
+  width: 54px;                /* gutter width */
+  overflow:hidden;
+  user-select:none;
+  text-align:right;
+  color: rgba(159,176,208,.85);
+  font-family: var(--mono);
+  font-size: 13px;
+  line-height: 1.35;
+  border-right: 1px solid rgba(255,255,255,.06);
+  background: rgba(0,0,0,.10);
+}
+
+#lineGutter .ln { display:block; }
+
+textarea#vhdlEditor{
+  overscroll-behavior-y: none;
+  flex:1;
+  height:100%;
+  padding:12px;
+  background: transparent; /* uses editorWrap background */
+  color:var(--text);
+  border:0;
+  outline:none;
+  resize:none;
+  font-family: var(--mono);
+  font-size: 13px;
+  line-height: 1.35;
+  overflow:auto;
+}
diff --git a/rtl/circuit copy._vhdl b/rtl/circuit copy._vhdl
new file mode 100644
index 0000000..20502cc
--- /dev/null
+++ b/rtl/circuit copy._vhdl	
@@ -0,0 +1,352 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Do not modify the following entity block
+entity circuit is
+port (
+  clk: in std_logic; 
+  key: in std_logic_vector(31 downto 0);   -- active low
+  sw: in std_logic_vector(31 downto 0);   -- active high
+  led: out std_logic_vector(31 downto 0);  -- active high
+  hex: out std_logic_vector(31 downto 0)  -- active low
+  );
+end circuit;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity alu is
+  Port (
+    func: in unsigned(3 downto 0);
+    a: in unsigned(7 downto 0);
+    b: in unsigned(7 downto 0);
+    carry_in: in std_logic;
+    o: out unsigned(7 downto 0);
+    carry_out: out std_logic;
+    zero: out std_logic;
+    gt: out std_logic;
+    lt: out std_logic;
+    eq: out std_logic
+  );
+end alu;
+
+architecture Behavioral of alu is
+    signal tmp: unsigned(8 downto 0) := "000000000";
+begin
+  with func select
+    tmp <=  ("0"&a) + ("0"&b) when x"0",
+          ("0"&a) + ("0"&b) + (x"00"&carry_in) when x"1",
+          ("0"&a) - ("0"&b) when x"2",
+          ("0"&a) - ("0"&b) - (x"00"&carry_in) when x"3",
+          ("0"&a) and ("0"&b) when x"4",
+          ("0"&a) or ("0"&b) when x"5",
+          ("0"&a) xor ("0"&b) when x"6",
+          "0"&x"00" when others;
+
+  zero <= '1' when tmp = 0 else '0';
+  eq <= '1' when a = b else '0';
+  lt <= '1' when a < b else '0';
+  gt <= '1' when a > b else '0';
+  carry_out <= tmp(8); 
+  o <= tmp(7 downto 0);
+
+end Behavioral ; -- Behavioral
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ram_8x256 is
+    Port (
+        clk   : in  std_logic;
+        we    : in  std_logic;  -- write enable
+        addr  : in  unsigned(7 downto 0); -- 8-bit address
+        din   : in  unsigned(7 downto 0); -- data input
+        dout  : out unsigned(7 downto 0)  -- data output
+    );
+end ram_8x256;
+
+architecture Behavioral of ram_8x256 is
+    type ram_type is array (0 to 255) of unsigned(7 downto 0);
+    signal ram : ram_type := (others => x"AB");
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if we = '1' then
+                ram(to_integer(unsigned(addr))) <= din;
+            end if;
+
+            dout <= ram(to_integer(unsigned(addr)));
+        end if;
+    end process;
+end Behavioral;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity inst_ram_8x256 is
+    Port (
+        clk   : in  std_logic;
+        addr  : in  unsigned(7 downto 0); -- 8-bit address
+        dout  : out unsigned(7 downto 0)  -- data output
+    );
+end inst_ram_8x256;
+
+architecture Behavioral of inst_ram_8x256 is
+    type ram_type is array (0 to 255) of unsigned(7 downto 0);
+    signal ram : ram_type := (
+      0 => x"A0", -- 0 => a
+      2 => x"B1", -- 1 => b
+      3 => x"10", -- a+b => out
+      4 => x"FE", -- out
+      5 => x"AE", -- out => a
+      6 => x"10", -- a+b => out
+      7 => x"FE", -- out
+      8 => x"BE", -- out => b
+      9 => x"D0", -- jump to 3
+      10 => x"03",
+      others => (others => '0')
+    );
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) or falling_edge(clk) then
+            dout <= ram(to_integer(unsigned(addr)));
+        end if;
+    end process;
+end Behavioral;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+architecture description of circuit is
+  signal clock: std_logic;
+
+  signal reg_pc: unsigned(7 downto 0) := "00000000";
+  signal reg_a: unsigned(7 downto 0) := "00000000";
+  signal reg_b: unsigned(7 downto 0) := "00000000";
+  signal reg_out: unsigned(7 downto 0) := "00000000";
+
+  signal inst_reg: unsigned(7 downto 0);
+  signal inst_bus: unsigned(7 downto 0);
+
+  signal data_read: unsigned(7 downto 0);
+  signal data_write: unsigned(7 downto 0) := "00000000";
+
+  signal data_addr: unsigned(7 downto 0) := "00000000";
+  signal data_write_e: std_logic := '0';
+
+  signal flag_carry: std_logic := '0';
+  signal flag_lt: std_logic := '0';
+  signal flag_gt: std_logic := '0';
+  signal flag_eq: std_logic := '0';
+  signal flag_zero: std_logic := '0';
+
+  signal alu_a, alu_b, alu_o : unsigned(7 downto 0) := "00000000";
+  signal alu_func : unsigned(3 downto 0) := "0000";
+  signal alu_carry, alu_zero, alu_gt, alu_lt, alu_eq : std_logic := '0';
+  signal alu_tmp: unsigned(8 downto 0) := "000000000";
+
+  function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
+    begin
+      case val is
+        when "0000"=> return "1000000"; --0
+        when "0001"=> return "1111001"; --1
+        when "0010"=> return "0100100"; --2
+        when "0011"=> return "0110000"; --3
+        when "0100"=> return "0011001"; --4
+        when "0101"=> return "0010010"; --5
+        when "0110"=> return "0000010"; --6
+        when "0111"=> return "1111000"; --7
+        when "1000"=> return "0000000"; --8
+        when "1001"=> return "0011000"; --9
+        when "1010"=> return "0001000"; --A
+        when "1011"=> return "0000011"; --B
+        when "1100"=> return "1000110"; --C
+        when "1101"=> return "0100001"; --D
+        when "1110"=> return "0000110"; --E
+        when "1111"=> return "0001110"; --F
+        when others=> return "1111111"; ---
+      end case;
+  end function;
+  
+
+begin
+
+  -- hex(7 downto 4) <= dec7seg(reg_out(7 downto 4));
+  -- hex(3 downto 0) <= dec7seg(reg_out(3 downto 0));
+
+  clock <= clk when sw(9) = '1' else sw(8);
+  
+  ram_inst : entity work.inst_ram_8x256
+    port map(
+        clk  => clk,
+        addr => reg_pc, 
+        dout => inst_bus
+    );
+
+  ram_data : entity work.ram_8x256
+    port map(
+        clk  => clk,
+        we   => data_write_e,
+        addr => data_addr,
+        din  => data_write,
+        dout => data_read
+    );
+
+      with alu_func select
+      alu_tmp <=  ("0"&alu_a) + ("0"&alu_b) when x"0",
+            ("0"&alu_a) + ("0"&alu_b) + (x"00"&flag_carry) when x"1",
+            ("0"&alu_a) - ("0"&alu_b) when x"2",
+            ("0"&alu_a) - ("0"&alu_b) - (x"00"&flag_carry) when x"3",
+            ("0"&alu_a) and ("0"&alu_b) when x"4",
+            ("0"&alu_a) or ("0"&alu_b) when x"5",
+            ("0"&alu_a) xor ("0"&alu_b) when x"6",
+            "0"&x"00" when others;
+
+    alu_zero <= '1' when alu_tmp = 0 else '0';
+    alu_eq <= '1' when alu_a = alu_b else '0';
+    alu_lt <= '1' when alu_a < alu_b else '0';
+    alu_gt <= '1' when alu_a > alu_b else '0';
+    alu_carry <= alu_tmp(8); 
+    alu_o <= alu_tmp(7 downto 0);
+
+    -- alu : entity work.alu
+    --   port map(
+    --     func      => alu_func,
+    --     a         => alu_a,
+    --     b         => alu_b,
+    --     carry_in  => flag_carry,
+    --     o         => alu_o,
+    --     carry_out => alu_carry,
+    --     zero      => alu_zero,
+    --     gt        => alu_gt,
+    --     lt        => alu_lt,
+    --     eq        => alu_eq
+    --   );
+
+  process(clock)
+    variable out_extended : unsigned(8 downto 0);
+  begin
+
+    if rising_edge(clock) then
+      inst_reg <= inst_bus;
+      data_write_e <= '0';
+
+      -- report "begin reg_a = " & integer'image(to_integer(unsigned(reg_a)))
+      -- & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
+      -- & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
+      -- & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
+      -- & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
+
+      -- alu operations a,b
+      if inst_bus(7 downto 4) = x"1" then
+        alu_func <= inst_bus(3 downto 0);
+        alu_a <= reg_a;
+        alu_b <= reg_b;
+        reg_out <= alu_o;
+      end if;
+      -- alu operations a,imm
+      if inst_bus(7 downto 4) = x"2" then
+        alu_func <= inst_bus(3 downto 0);
+        alu_a <= reg_a;
+        alu_b <= x"00";
+        reg_pc <= reg_pc+1;
+      end if;
+      -- alu operations imm,b
+      if inst_bus(7 downto 4) = x"3" then
+        alu_func <= inst_bus(3 downto 0);
+        alu_a <= x"00";
+        alu_b <= reg_b;
+        reg_pc <= reg_pc+1;
+      end if;
+
+      case inst_bus is
+        -- nop
+        when x"00" => null;
+
+        -- 0 => a
+        when x"A0" => reg_a <= x"00";
+        -- 1 => a
+        when x"A1" => reg_a <= x"01";
+        -- mem[reg b] => a 
+        when x"AC" =>
+         data_addr <= reg_b;
+        -- out => a
+        when x"AE" => reg_a <= reg_out;
+        -- immediate => a
+        when x"AF" => reg_pc <= reg_pc+1;
+
+        -- 0 => b
+        when x"B0" => reg_b <= x"00";
+        -- 1 => b
+        when x"B1" => reg_b <= x"01";
+        -- mem[reg a] => b 
+        when x"BC" => 
+         data_addr <= reg_b;
+        -- out => b
+        when x"BE" => reg_b <= reg_out;
+        -- immediate => b
+        when x"BF" => reg_pc <= reg_pc+1;
+
+        -- conditional
+
+        -- jump imm addr abs
+        when x"D0" => reg_pc <= reg_pc+1;
+        -- jump imm addr rel
+        when x"D1" => reg_pc <= reg_pc+1;
+        -- jump addr reg a
+        when x"DA" => reg_pc <= reg_a-1;
+        -- jump addr reg b
+        when x"DB" => reg_pc <= reg_b-1;
+
+        -- out
+        when x"FE" => report " out = " & integer'image(to_integer(unsigned(reg_out)));
+        -- halt
+        when x"FF" => reg_pc <= reg_pc-1;
+
+        when others =>  null;
+      end case;
+    end if;
+
+    if falling_edge(clock) then
+      case inst_reg is
+        when x"AC" => reg_a <= data_read;
+        when x"AF" => reg_a <= inst_bus;
+
+        when x"BC" => reg_b <= data_read;
+        when x"BF" => reg_b <= inst_bus;
+
+        when others => null;
+      end case;
+
+
+      case inst_reg is
+        -- jump imm addr abs
+        when x"D0" => reg_pc <= inst_bus;
+        -- jump imm addr rel
+        when x"D1" => reg_pc <= reg_pc+inst_bus;
+
+        when others => reg_pc <= reg_pc+1;
+      end case;
+
+      --       report "end reg_a = " & integer'image(to_integer(unsigned(reg_a)))
+      -- & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
+      -- & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
+      -- & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
+      -- & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
+      
+
+    end if;
+    
+  end process;
+end description;
\ No newline at end of file
diff --git a/rtl/circuit._vhdl b/rtl/circuit._vhdl
index ef367ed..9da6efc 100644
--- a/rtl/circuit._vhdl
+++ b/rtl/circuit._vhdl
@@ -6,19 +6,18 @@ use ieee.numeric_std.all;
 entity circuit is
 port (
   clk: in std_logic; -- 500 Hz, period 2 ms
-  key: in std_logic_vector(3 downto 0);   -- active low
-  sw: in std_logic_vector(9 downto 0);   -- active high
-  led: out std_logic_vector(9 downto 0) := (others => '0');  -- active high
-  hex0: out std_logic_vector(6 downto 0) := (others => '0');  -- active low
-  hex1: out std_logic_vector(6 downto 0) := (others => '0')  -- active low
+  key: in std_logic_vector(31 downto 0);   -- active low
+  sw: in std_logic_vector(31 downto 0);   -- active high
+  led: out std_logic_vector(31 downto 0) := (others => '0');  -- active high
+  hex: out std_logic_vector(31 downto 0) := (others => '0')  -- active low
   );
 end circuit;
 
 
 architecture description of circuit is
-  signal counter: unsigned(9 downto 0) := "0000000000";
+  signal counter: unsigned(31 downto 0) := x"00000000";
 begin
-  led <= std_logic_vector(counter(9 downto 0));
+  led <= std_logic_vector(counter);
   process(clk)
   begin
     counter <= counter+1;
diff --git a/rtl/circuit.vhdl b/rtl/circuit.vhdl
index 72c6944..1efbfc2 100644
--- a/rtl/circuit.vhdl
+++ b/rtl/circuit.vhdl
@@ -5,325 +5,23 @@ use ieee.numeric_std.all;
 -- Do not modify the following entity block
 entity circuit is
 port (
-  clk: in std_logic; 
+  clk: in std_logic; -- 500 Hz, period 2 ms
   key: in std_logic_vector(31 downto 0);   -- active low
   sw: in std_logic_vector(31 downto 0);   -- active high
-  led: out std_logic_vector(31 downto 0);  -- active high
-  hex: out std_logic_vector(31 downto 0)  -- active low
+  led: out std_logic_vector(31 downto 0) := (others => '0');  -- active high
+  hex: out std_logic_vector(31 downto 0) := (others => '0')  -- active low
   );
 end circuit;
 
 
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity alu is
-  Port (
-    func: in unsigned(3 downto 0);
-    a: in unsigned(7 downto 0);
-    b: in unsigned(7 downto 0);
-    carry_in: in std_logic;
-    o: out unsigned(7 downto 0);
-    carry_out: out std_logic;
-    zero: out std_logic;
-    gt: out std_logic;
-    lt: out std_logic;
-    eq: out std_logic
-  );
-end alu;
-
-architecture Behavioral of alu is
-    signal tmp: unsigned(8 downto 0);
-begin
-  with func select
-    tmp <=  ("0"&a) + ("0"&b) when x"0",
-          ("0"&a) + ("0"&b) + (x"00"&carry_in) when x"1",
-          ("0"&a) - ("0"&b) when x"2",
-          ("0"&a) - ("0"&b) - (x"00"&carry_in) when x"3",
-          ("0"&a) and ("0"&b) when x"4",
-          ("0"&a) or ("0"&b) when x"5",
-          ("0"&a) xor ("0"&b) when x"6",
-          "0"&x"00" when others;
-
-  zero <= '1' when tmp = 0 else '0';
-  eq <= '1' when a = b else '0';
-  lt <= '1' when a < b else '0';
-  gt <= '1' when a > b else '0';
-  carry_out <= tmp(8); 
-  o <= tmp(7 downto 0);
-
-end Behavioral ; -- Behavioral
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity ram_8x256 is
-    Port (
-        clk   : in  std_logic;
-        we    : in  std_logic;  -- write enable
-        addr  : in  unsigned(7 downto 0); -- 8-bit address
-        din   : in  unsigned(7 downto 0); -- data input
-        dout  : out unsigned(7 downto 0)  -- data output
-    );
-end ram_8x256;
-
-architecture Behavioral of ram_8x256 is
-    type ram_type is array (0 to 255) of unsigned(7 downto 0);
-    signal ram : ram_type := (others => x"AB");
-begin
-    process(clk)
-    begin
-        if rising_edge(clk) then
-            if we = '1' then
-                ram(to_integer(unsigned(addr))) <= din;
-            end if;
-
-            dout <= ram(to_integer(unsigned(addr)));
-        end if;
-    end process;
-end Behavioral;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity inst_ram_8x256 is
-    Port (
-        clk   : in  std_logic;
-        addr  : in  unsigned(7 downto 0); -- 8-bit address
-        dout  : out unsigned(7 downto 0)  -- data output
-    );
-end inst_ram_8x256;
-
-architecture Behavioral of inst_ram_8x256 is
-    type ram_type is array (0 to 255) of unsigned(7 downto 0);
-    signal ram : ram_type := (
-      0 => x"A0", -- 0 => a
-      2 => x"B1", -- 1 => b
-      3 => x"10", -- a+b => out
-      4 => x"AE", -- out => a
-      5 => x"10", -- a+b => out
-      6 => x"BE", -- out => b
-      7 => x"D0", -- jump to 3
-      8 => x"03",
-      others => (others => '0')
-    );
-begin
-    process(clk)
-    begin
-        if rising_edge(clk) or falling_edge(clk) then
-            dout <= ram(to_integer(unsigned(addr)));
-        end if;
-    end process;
-end Behavioral;
-
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-
 architecture description of circuit is
-  signal clock: std_logic;
-
-  signal reg_pc: unsigned(7 downto 0) := "00000000";
-  signal reg_a: unsigned(7 downto 0) := "00000000";
-  signal reg_b: unsigned(7 downto 0) := "00000000";
-  signal reg_out: unsigned(7 downto 0) := "00000000";
-
-  signal inst_reg: unsigned(7 downto 0);
-  signal inst_bus: unsigned(7 downto 0);
-
-  signal data_read: unsigned(7 downto 0);
-  signal data_write: unsigned(7 downto 0);
-
-  signal data_addr: unsigned(7 downto 0) := "00000000";
-  signal data_write_e: std_logic := '0';
-
-  signal flag_carry: std_logic := '0';
-  signal flag_lt: std_logic := '0';
-  signal flag_gt: std_logic := '0';
-  signal flag_eq: std_logic := '0';
-  signal flag_zero: std_logic := '0';
-
-  signal alu_a, alu_b, alu_o : unsigned(7 downto 0);
-  signal alu_func : unsigned(3 downto 0);
-  signal alu_carry, alu_zero, alu_gt, alu_lt, alu_eq : std_logic;
-
-  function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
-    begin
-      case val is
-        when "0000"=> return "1000000"; --0
-        when "0001"=> return "1111001"; --1
-        when "0010"=> return "0100100"; --2
-        when "0011"=> return "0110000"; --3
-        when "0100"=> return "0011001"; --4
-        when "0101"=> return "0010010"; --5
-        when "0110"=> return "0000010"; --6
-        when "0111"=> return "1111000"; --7
-        when "1000"=> return "0000000"; --8
-        when "1001"=> return "0011000"; --9
-        when "1010"=> return "0001000"; --A
-        when "1011"=> return "0000011"; --B
-        when "1100"=> return "1000110"; --C
-        when "1101"=> return "0100001"; --D
-        when "1110"=> return "0000110"; --E
-        when "1111"=> return "0001110"; --F
-        when others=> return "1111111"; ---
-      end case;
-  end function;
-  
-
+  signal counter: unsigned(9 downto 0) := "0000000000";
 begin
-
-  -- hex(7 downto 4) <= dec7seg(reg_out(7 downto 4));
-  -- hex(3 downto 0) <= dec7seg(reg_out(3 downto 0));
-
-  clock <= clk when sw(9) = '1' else sw(8);
-  
-  ram_inst : entity work.inst_ram_8x256
-    port map(
-        clk  => clk,
-        addr => reg_pc, 
-        dout => inst_bus
-    );
-
-  ram_data : entity work.ram_8x256
-    port map(
-        clk  => clk,
-        we   => data_write_e,
-        addr => data_addr,
-        din  => data_write,
-        dout => data_read
-    );
-
-    alu : entity work.alu
-      port map(
-        func      => alu_func,
-        a         => alu_a,
-        b         => alu_b,
-        carry_in  => flag_carry,
-        o         => alu_o,
-        carry_out => alu_carry,
-        zero      => alu_zero,
-        gt        => alu_gt,
-        lt        => alu_lt,
-        eq        => alu_eq
-      );
-
-  process(clock)
-    variable out_extended : unsigned(8 downto 0);
+  led(9 downto 0) <= std_logic_vector(counter);
+  -- led(10) <= clk;
+  process(sw(0))
   begin
-
-    if rising_edge(clock) then
-      inst_reg <= inst_bus;
-      data_write_e <= '0';
-
-      report "begin reg_a = " & integer'image(to_integer(unsigned(reg_a)))
-      & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
-      & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
-      & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
-      & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
-
-      -- alu operations a,b
-      if inst_reg(7 downto 4) = x"1" then
-        alu_func <= inst_reg(3 downto 0);
-        alu_a <= reg_a;
-        alu_b <= reg_b;
-        reg_out <= alu_o;
-      end if;
-      -- alu operations a,imm
-      if inst_reg(7 downto 4) = x"2" then
-        alu_func <= inst_reg(3 downto 0);
-        alu_a <= reg_a;
-        reg_pc <= reg_pc+1;
-      end if;
-      -- alu operations imm,b
-      if inst_reg(7 downto 4) = x"3" then
-        alu_func <= inst_reg(3 downto 0);
-        alu_b <= reg_b;
-        reg_pc <= reg_pc+1;
-      end if;
-
-      case inst_bus is
-        -- nop
-        when x"00" => null;
-
-
-        -- 0 => a
-        when x"A0" => reg_a <= x"00";
-        -- 1 => a
-        when x"A1" => reg_a <= x"01";
-        -- mem[reg b] => a 
-        when x"AC" =>
-         data_addr <= reg_b;
-        -- out => a
-        when x"AE" => reg_a <= reg_out;
-        -- immediate => a
-        when x"AF" => reg_pc <= reg_pc+1;
-
-        -- 0 => b
-        when x"B0" => reg_b <= x"00";
-        -- 1 => b
-        when x"B1" => reg_b <= x"01";
-        -- mem[reg a] => b 
-        when x"BC" => 
-         data_addr <= reg_b;
-        -- out => b
-        when x"BE" => reg_b <= reg_out;
-        -- immediate => b
-        when x"BF" => reg_pc <= reg_pc+1;
-
-        -- conditional
-
-        -- jump imm addr abs
-        when x"D0" => reg_pc <= reg_pc+1;
-        -- jump imm addr rel
-        when x"D1" => reg_pc <= reg_pc+1;
-        -- jump addr reg a
-        when x"DA" => reg_pc <= reg_a-1;
-        -- jump addr reg b
-        when x"DB" => reg_pc <= reg_b-1;
-
-        -- halt
-        when x"FF" => reg_pc <= reg_pc-1;
-
-        when others =>  null;
-      end case;
-    end if;
-
-    if falling_edge(clock) then
-      case inst_reg is
-        when x"AC" => reg_a <= data_read;
-        when x"AF" => reg_a <= inst_bus;
-
-        when x"BC" => reg_b <= data_read;
-        when x"BF" => reg_b <= inst_bus;
-
-        when others => null;
-      end case;
-
-
-      case inst_reg is
-        -- jump imm addr abs
-        when x"D0" => reg_pc <= inst_bus;
-        -- jump imm addr rel
-        when x"D1" => reg_pc <= reg_pc+inst_bus;
-
-        when others => reg_pc <= reg_pc+1;
-      end case;
-
-            report "end reg_a = " & integer'image(to_integer(unsigned(reg_a)))
-      & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
-      & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
-      & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
-      & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
-      
-
-    end if;
-    
+    counter <= counter+1;
+    report "meow";
   end process;
 end description;
\ No newline at end of file
diff --git a/rtl/tb.vhdl b/rtl/tb.vhdl
index 6831d75..4df30f2 100644
--- a/rtl/tb.vhdl
+++ b/rtl/tb.vhdl
@@ -71,18 +71,18 @@ begin
     variable sw_i  : integer;
     variable key_i : integer;
   begin
-    ffi_init;               -- starts Rust listener thread
+    ffi_init;
     wait for 0 ns;
-
     
     while true loop
       wait until rising_edge(clk) or falling_edge(clk);
+      wait for 0 ns;
 
       sw_i  := ffi_get_sw;
       key_i := ffi_get_key;
 
-      sw  <= std_logic_vector(to_unsigned(sw_i, 32));
-      key <= std_logic_vector(to_unsigned(key_i, 32));
+      sw  <= std_logic_vector(to_signed(sw_i, 32));
+      key <= std_logic_vector(to_signed(key_i, 32));
 
       ffi_set_outputs(
           to_integer(unsigned(clean_slv(led))),
diff --git a/run.sh b/run.sh
index 56c3e0f..3cfef6f 100755
--- a/run.sh
+++ b/run.sh
@@ -3,7 +3,6 @@ set -euo pipefail
 
 mkdir -p build
 
-# Build Rust shared library
 pushd conn >/dev/null
 cargo build --release
 popd >/dev/null
@@ -14,21 +13,10 @@ LIBSRC="../conn/target/release/libvhdl_ui.a"
 LIBDIR="../conn/target/release"
 
 
-ghdl -a --std=08 ../rtl/*.vhdl
+ghdl -a -g --std=08 ../rtl/*.vhdl
 
 ghdl -e --std=08 \
-  -Wl,"$LIBSRC" \
-  -Wl,-Wl,-rpath -Wl,-Wl,$LIBDIR \
-   tb
+  -Wl,$LIBSRC \
+  tb
 
-
-echo "=== Running sim ==="
-echo "Connect and stream inputs using:"
-echo "  nc 127.0.0.1 5555"
-echo "Then type lines like:"
-echo "  sw=1"
-echo "  key=15"
-echo "  key=7   (press KEY3 if bit3 becomes 0, etc; active-low)"
-echo
-
-ghdl -r --std=08 tb
\ No newline at end of file
+ghdl -r --std=08 tb --stop-delta=2147483647
\ No newline at end of file
diff --git a/run_relay.sh b/run_relay.sh
new file mode 100755
index 0000000..2846bf1
--- /dev/null
+++ b/run_relay.sh
@@ -0,0 +1,11 @@
+#!/usr/bin/env bash
+set -euo pipefail
+
+pushd conn >/dev/null
+cargo build --release
+popd >/dev/null
+
+
+pushd relay >/dev/null
+cargo run --release
+popd >/dev/null
\ No newline at end of file