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39 lines
980 B
VHDL
39 lines
980 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity inst_ram_8x256 is
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Port (
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clk : in std_logic;
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addr : in unsigned(7 downto 0); -- 8-bit address
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dout : out unsigned(7 downto 0) -- data output
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);
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end inst_ram_8x256;
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architecture Behavioral of inst_ram_8x256 is
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type ram_type is array (0 to 255) of unsigned(7 downto 0);
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signal ram : ram_type := (
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0 => x"A0", -- 0 => a
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1 => x"B1", -- 1 => b
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2 => x"10", -- a+b => out
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3 => x"FE", -- out
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4 => x"AE", -- out => a
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5 => x"01", -- swap a/b
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6 => x"3F", -- cmp 144, b
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7 => x"90",
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8 => x"C7", -- jump to 2 if 144 <= b
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9 => x"02",
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10 => x"FF", -- halt
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others => (others => '0')
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);
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begin
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process(clk)
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begin
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if rising_edge(clk) or falling_edge(clk) then
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dout <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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end Behavioral;
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