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32 lines
753 B
Verilog
32 lines
753 B
Verilog
module seg_plex (
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input wire clk,
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input wire [63:0] seg0,
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input wire [63:0] seg1,
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input wire [63:0] seg2,
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input wire [63:0] seg3,
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output reg [31:0] segv,
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output reg [2:0] segs
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);
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reg [2:0] counter = 3'b000;
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always @(posedge clk) begin
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case (counter)
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3'd0: segv <= seg0[31:0];
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3'd1: segv <= seg0[63:32];
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3'd2: segv <= seg1[31:0];
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3'd3: segv <= seg1[63:32];
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3'd4: segv <= seg2[31:0];
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3'd5: segv <= seg2[63:32];
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3'd6: segv <= seg3[31:0];
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3'd7: segv <= seg3[63:32];
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default: segv <= 32'b0;
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endcase
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counter <= counter + 3'd1;
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segs <= counter;
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end
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endmodule
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