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55 lines
1.8 KiB
Verilog
55 lines
1.8 KiB
Verilog
module keypad_input (
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input wire clk,
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input wire [7:0] keypad,
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output reg [3:0] dig,
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output reg dig_e,
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output reg dot,
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output reg eq,
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output reg [3:0] op,
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output reg op_e
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);
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reg [7:0] keypad_curr = 8'b00000000;
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always @(posedge clk or negedge clk) begin
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if (clk && (keypad != keypad_curr)) begin
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case (keypad)
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8'b10001000: begin op <= 4'b0001; op_e <= 1'b1; end
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8'b10000100: begin eq <= 1'b1; end
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8'b10000010: begin dot <= 1'b1; end
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8'b10000001: begin dig <= 4'b0000; dig_e <= 1'b1; end
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8'b01001000: begin op <= 4'b0010; op_e <= 1'b1; end
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8'b01000100: begin dig <= 4'b0011; dig_e <= 1'b1; end
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8'b01000010: begin dig <= 4'b0010; dig_e <= 1'b1; end
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8'b01000001: begin dig <= 4'b0001; dig_e <= 1'b1; end
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8'b00101000: begin op <= 4'b0011; op_e <= 1'b1; end
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8'b00100100: begin dig <= 4'b0110; dig_e <= 1'b1; end
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8'b00100010: begin dig <= 4'b0101; dig_e <= 1'b1; end
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8'b00100001: begin dig <= 4'b0100; dig_e <= 1'b1; end
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8'b00011000: begin op <= 4'b0100; op_e <= 1'b1; end
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8'b00010100: begin dig <= 4'b1000; dig_e <= 1'b1; end
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8'b00010010: begin dig <= 4'b1000; dig_e <= 1'b1; end
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8'b00010001: begin dig <= 4'b0111; dig_e <= 1'b1; end
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default: begin end
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endcase
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keypad_curr <= keypad;
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end
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if (!clk && (keypad != keypad_curr)) begin
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dig <= 4'b0000;
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dig_e <= 1'b0;
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eq <= 1'b0;
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dot <= 1'b0;
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op <= 4'b0000;
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op_e <= 1'b0;
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end
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end
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endmodule
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