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81 lines
2.2 KiB
Verilog
81 lines
2.2 KiB
Verilog
module bcd (
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input wire clk,
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input wire signed [22:0] num, // sfixed(15 downto -7)
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input wire en,
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output reg [63:0] seg
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);
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function [7:0] seg_encode;
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input [3:0] d;
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begin
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case (d)
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4'd0: seg_encode = 8'b00111111;
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4'd1: seg_encode = 8'b00000110;
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4'd2: seg_encode = 8'b01011011;
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4'd3: seg_encode = 8'b01001111;
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4'd4: seg_encode = 8'b01100110;
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4'd5: seg_encode = 8'b01101101;
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4'd6: seg_encode = 8'b01111101;
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4'd7: seg_encode = 8'b00000111;
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4'd8: seg_encode = 8'b01111111;
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4'd9: seg_encode = 8'b01101111;
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default: seg_encode = 8'b00000000;
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endcase
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end
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endfunction
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integer scaled_hundredths;
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integer magnitude;
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integer frac_hundredths;
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integer tmp;
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integer j;
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reg negative;
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reg [3:0] digits [0:7];
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reg [63:0] out_seg;
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always @* begin
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if (!en) begin
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seg = 64'b0;
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end else begin
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out_seg = 64'b0;
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// num is Q16.7 fixed-point, so value = num / 128.
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// Round to nearest hundredth.
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if (num < 0) begin
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scaled_hundredths = ((num * 100) - 64) / 128;
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end else begin
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scaled_hundredths = ((num * 100) + 64) / 128;
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end
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negative = (scaled_hundredths < 0);
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if (negative) begin
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magnitude = -scaled_hundredths;
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end else begin
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magnitude = scaled_hundredths;
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end
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frac_hundredths = magnitude % 100;
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tmp = magnitude;
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for (j = 0; j < 8; j = j + 1) begin
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integer dig = tmp % 10;
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digits[j] = dig[3:0];
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tmp = tmp / 10;
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end
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for (j = 0; j < 7; j = j + 1) begin
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out_seg[(7 - j) * 8 +: 8] = seg_encode(digits[j]);
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end
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out_seg[5 * 8 + 7] = 1'b1;
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if (negative) begin
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out_seg[6] = 1'b1;
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end
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seg = out_seg;
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end
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end
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endmodule
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