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27 lines
No EOL
740 B
VHDL
27 lines
No EOL
740 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic; -- 500 Hz, period 2 ms
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key: in std_logic_vector(31 downto 0); -- active low
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sw: in std_logic_vector(31 downto 0); -- active high
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led: out std_logic_vector(31 downto 0) := (others => '0'); -- active high
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hex: out std_logic_vector(31 downto 0) := (others => '0') -- active low
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);
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end circuit;
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architecture description of circuit is
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signal counter: unsigned(9 downto 0) := "0000000000";
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begin
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led(9 downto 0) <= std_logic_vector(counter);
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-- led(10) <= clk;
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process(sw(0))
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begin
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counter <= counter+1;
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report "meow";
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end process;
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end description; |