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26 lines
No EOL
647 B
VHDL
26 lines
No EOL
647 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic; -- 500 Hz, period 2 ms
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btn: in std_logic_vector(31 downto 0);
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sw: in std_logic_vector(31 downto 0);
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led: out std_logic_vector(31 downto 0) := (others => '0');
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segv: out std_logic_vector(31 downto 0);
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segs: out std_logic_vector(31 downto 0)
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);
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end circuit;
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architecture description of circuit is
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signal counter: unsigned(31 downto 0) := x"00000000";
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begin
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led <= std_logic_vector(counter);
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process(clk)
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begin
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counter <= counter+1;
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end process;
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end description; |