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19 lines
503 B
Verilog
19 lines
503 B
Verilog
// Do not modify the following module interface.
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module circuit (
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input wire clk, // 500 Hz, period 2 ms
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input wire [31:0] btn,
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input wire [31:0] sw,
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output reg [31:0] led = 32'h00000000,
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output wire [31:0] segv,
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output wire [31:0] segs
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);
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reg [31:0] counter = 32'h00000000;
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assign segv = 32'h00000000;
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assign segs = 32'h00000000;
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always @(posedge clk) begin
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counter <= counter + 32'd1;
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led <= counter ^ sw ^ btn;
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end
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endmodule
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