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updated verilog example

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ParkerTenBroeck 2026-03-13 13:51:03 -04:00
parent c3a3e89082
commit f1f57c66fd
1 changed files with 2 additions and 22 deletions
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24
src_verilog/bcd.v
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@ -24,27 +24,6 @@ module bcd (
end end
endfunction endfunction
function [3:0] to_bcd_digit;
input integer value;
integer remainder;
begin
remainder = value % 10;
case (remainder)
0: to_bcd_digit = 4'd0;
1: to_bcd_digit = 4'd1;
2: to_bcd_digit = 4'd2;
3: to_bcd_digit = 4'd3;
4: to_bcd_digit = 4'd4;
5: to_bcd_digit = 4'd5;
6: to_bcd_digit = 4'd6;
7: to_bcd_digit = 4'd7;
8: to_bcd_digit = 4'd8;
9: to_bcd_digit = 4'd9;
default: to_bcd_digit = 4'd0;
endcase
end
endfunction
integer scaled_hundredths; integer scaled_hundredths;
integer magnitude; integer magnitude;
integer frac_hundredths; integer frac_hundredths;
@ -80,7 +59,8 @@ module bcd (
tmp = magnitude; tmp = magnitude;
for (j = 0; j < 8; j = j + 1) begin for (j = 0; j < 8; j = j + 1) begin
digits[j] = to_bcd_digit(tmp); integer dig = tmp % 10;
digits[j] = dig[3:0];
tmp = tmp / 10; tmp = tmp / 10;
end end