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added verilog support

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ParkerTenBroeck 2026-03-13 13:28:26 -04:00
parent 5746846896
commit c3a3e89082
20 changed files with 633 additions and 88 deletions
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32
src_verilog/seg_plex.v Normal file
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module seg_plex (
input wire clk,
input wire [63:0] seg0,
input wire [63:0] seg1,
input wire [63:0] seg2,
input wire [63:0] seg3,
output reg [31:0] segv,
output reg [2:0] segs
);
reg [2:0] counter = 3'b000;
always @(posedge clk) begin
case (counter)
3'd0: segv <= seg0[31:0];
3'd1: segv <= seg0[63:32];
3'd2: segv <= seg1[31:0];
3'd3: segv <= seg1[63:32];
3'd4: segv <= seg2[31:0];
3'd5: segv <= seg2[63:32];
3'd6: segv <= seg3[31:0];
3'd7: segv <= seg3[63:32];
default: segv <= 32'b0;
endcase
counter <= counter + 3'd1;
segs <= counter;
end
endmodule