mirror of
https://github.com/ParkerTenBroeck/hdl_sim.git
synced 2026-06-06 21:24:06 -04:00
added verilog support
This commit is contained in:
ParkerTenBroeck
parent
5746846896
commit
c3a3e89082
20 changed files with 633 additions and 88 deletions
101
src_verilog/bcd.v
Normal file
101
src_verilog/bcd.v
Normal file
|
|
@ -0,0 +1,101 @@
|
|||
module bcd (
|
||||
input wire clk,
|
||||
input wire signed [22:0] num, // sfixed(15 downto -7)
|
||||
input wire en,
|
||||
output reg [63:0] seg
|
||||
);
|
||||
|
||||
function [7:0] seg_encode;
|
||||
input [3:0] d;
|
||||
begin
|
||||
case (d)
|
||||
4'd0: seg_encode = 8'b00111111;
|
||||
4'd1: seg_encode = 8'b00000110;
|
||||
4'd2: seg_encode = 8'b01011011;
|
||||
4'd3: seg_encode = 8'b01001111;
|
||||
4'd4: seg_encode = 8'b01100110;
|
||||
4'd5: seg_encode = 8'b01101101;
|
||||
4'd6: seg_encode = 8'b01111101;
|
||||
4'd7: seg_encode = 8'b00000111;
|
||||
4'd8: seg_encode = 8'b01111111;
|
||||
4'd9: seg_encode = 8'b01101111;
|
||||
default: seg_encode = 8'b00000000;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [3:0] to_bcd_digit;
|
||||
input integer value;
|
||||
integer remainder;
|
||||
begin
|
||||
remainder = value % 10;
|
||||
case (remainder)
|
||||
0: to_bcd_digit = 4'd0;
|
||||
1: to_bcd_digit = 4'd1;
|
||||
2: to_bcd_digit = 4'd2;
|
||||
3: to_bcd_digit = 4'd3;
|
||||
4: to_bcd_digit = 4'd4;
|
||||
5: to_bcd_digit = 4'd5;
|
||||
6: to_bcd_digit = 4'd6;
|
||||
7: to_bcd_digit = 4'd7;
|
||||
8: to_bcd_digit = 4'd8;
|
||||
9: to_bcd_digit = 4'd9;
|
||||
default: to_bcd_digit = 4'd0;
|
||||
endcase
|
||||
end
|
||||
endfunction
|
||||
|
||||
integer scaled_hundredths;
|
||||
integer magnitude;
|
||||
integer frac_hundredths;
|
||||
integer tmp;
|
||||
integer j;
|
||||
reg negative;
|
||||
reg [3:0] digits [0:7];
|
||||
reg [63:0] out_seg;
|
||||
|
||||
always @* begin
|
||||
if (!en) begin
|
||||
seg = 64'b0;
|
||||
end else begin
|
||||
out_seg = 64'b0;
|
||||
|
||||
// num is Q16.7 fixed-point, so value = num / 128.
|
||||
// Round to nearest hundredth.
|
||||
if (num < 0) begin
|
||||
scaled_hundredths = ((num * 100) - 64) / 128;
|
||||
end else begin
|
||||
scaled_hundredths = ((num * 100) + 64) / 128;
|
||||
end
|
||||
|
||||
negative = (scaled_hundredths < 0);
|
||||
|
||||
if (negative) begin
|
||||
magnitude = -scaled_hundredths;
|
||||
end else begin
|
||||
magnitude = scaled_hundredths;
|
||||
end
|
||||
|
||||
frac_hundredths = magnitude % 100;
|
||||
tmp = magnitude;
|
||||
|
||||
for (j = 0; j < 8; j = j + 1) begin
|
||||
digits[j] = to_bcd_digit(tmp);
|
||||
tmp = tmp / 10;
|
||||
end
|
||||
|
||||
for (j = 0; j < 7; j = j + 1) begin
|
||||
out_seg[(7 - j) * 8 +: 8] = seg_encode(digits[j]);
|
||||
end
|
||||
|
||||
out_seg[5 * 8 + 7] = 1'b1;
|
||||
|
||||
if (negative) begin
|
||||
out_seg[6] = 1'b1;
|
||||
end
|
||||
|
||||
seg = out_seg;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
56
src_verilog/example.v
Normal file
56
src_verilog/example.v
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
// Do not modify the following module interface.
|
||||
module circuit (
|
||||
input wire clk, // 500 Hz, period 2 ms
|
||||
input wire [31:0] btn,
|
||||
input wire [31:0] sw,
|
||||
output wire [31:0] led,
|
||||
output wire [31:0] segv,
|
||||
output wire [31:0] segs
|
||||
);
|
||||
|
||||
wire [3:0] dig;
|
||||
wire dig_e;
|
||||
wire dot;
|
||||
wire eq;
|
||||
wire [3:0] op;
|
||||
wire op_e;
|
||||
|
||||
wire [63:0] seg_a;
|
||||
wire [2:0] segs_mux;
|
||||
wire signed [22:0] sw_fixed;
|
||||
|
||||
assign led = 32'b0;
|
||||
assign segs = {29'b0, segs_mux};
|
||||
|
||||
// Convert signed 16-bit integer to signed Q16.7 fixed-point.
|
||||
assign sw_fixed = {sw[15:0], 7'b0};
|
||||
|
||||
keypad_input keypad_input_inst (
|
||||
.clk(clk),
|
||||
.keypad(btn[15:8]),
|
||||
.dig(dig),
|
||||
.dig_e(dig_e),
|
||||
.dot(dot),
|
||||
.eq(eq),
|
||||
.op(op),
|
||||
.op_e(op_e)
|
||||
);
|
||||
|
||||
bcd bcd_inst (
|
||||
.clk(clk),
|
||||
.num(sw_fixed),
|
||||
.en(1'b1),
|
||||
.seg(seg_a)
|
||||
);
|
||||
|
||||
seg_plex seg_plex_inst (
|
||||
.clk(clk),
|
||||
.seg0(seg_a),
|
||||
.seg1(64'h0000000000000000),
|
||||
.seg2(64'h0000000000000000),
|
||||
.seg3(64'h0000000000000000),
|
||||
.segv(segv),
|
||||
.segs(segs_mux)
|
||||
);
|
||||
|
||||
endmodule
|
||||
55
src_verilog/keypad_input.v
Normal file
55
src_verilog/keypad_input.v
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
module keypad_input (
|
||||
input wire clk,
|
||||
input wire [7:0] keypad,
|
||||
|
||||
output reg [3:0] dig,
|
||||
output reg dig_e,
|
||||
|
||||
output reg dot,
|
||||
output reg eq,
|
||||
|
||||
output reg [3:0] op,
|
||||
output reg op_e
|
||||
);
|
||||
|
||||
reg [7:0] keypad_curr = 8'b00000000;
|
||||
|
||||
always @(posedge clk or negedge clk) begin
|
||||
if (clk && (keypad != keypad_curr)) begin
|
||||
case (keypad)
|
||||
8'b10001000: begin op <= 4'b0001; op_e <= 1'b1; end
|
||||
8'b10000100: begin eq <= 1'b1; end
|
||||
8'b10000010: begin dot <= 1'b1; end
|
||||
8'b10000001: begin dig <= 4'b0000; dig_e <= 1'b1; end
|
||||
|
||||
8'b01001000: begin op <= 4'b0010; op_e <= 1'b1; end
|
||||
8'b01000100: begin dig <= 4'b0011; dig_e <= 1'b1; end
|
||||
8'b01000010: begin dig <= 4'b0010; dig_e <= 1'b1; end
|
||||
8'b01000001: begin dig <= 4'b0001; dig_e <= 1'b1; end
|
||||
|
||||
8'b00101000: begin op <= 4'b0011; op_e <= 1'b1; end
|
||||
8'b00100100: begin dig <= 4'b0110; dig_e <= 1'b1; end
|
||||
8'b00100010: begin dig <= 4'b0101; dig_e <= 1'b1; end
|
||||
8'b00100001: begin dig <= 4'b0100; dig_e <= 1'b1; end
|
||||
|
||||
8'b00011000: begin op <= 4'b0100; op_e <= 1'b1; end
|
||||
8'b00010100: begin dig <= 4'b1000; dig_e <= 1'b1; end
|
||||
8'b00010010: begin dig <= 4'b1000; dig_e <= 1'b1; end
|
||||
8'b00010001: begin dig <= 4'b0111; dig_e <= 1'b1; end
|
||||
|
||||
default: begin end
|
||||
endcase
|
||||
keypad_curr <= keypad;
|
||||
end
|
||||
|
||||
if (!clk && (keypad != keypad_curr)) begin
|
||||
dig <= 4'b0000;
|
||||
dig_e <= 1'b0;
|
||||
eq <= 1'b0;
|
||||
dot <= 1'b0;
|
||||
op <= 4'b0000;
|
||||
op_e <= 1'b0;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
32
src_verilog/seg_plex.v
Normal file
32
src_verilog/seg_plex.v
Normal file
|
|
@ -0,0 +1,32 @@
|
|||
module seg_plex (
|
||||
input wire clk,
|
||||
|
||||
input wire [63:0] seg0,
|
||||
input wire [63:0] seg1,
|
||||
input wire [63:0] seg2,
|
||||
input wire [63:0] seg3,
|
||||
|
||||
output reg [31:0] segv,
|
||||
output reg [2:0] segs
|
||||
);
|
||||
|
||||
reg [2:0] counter = 3'b000;
|
||||
|
||||
always @(posedge clk) begin
|
||||
case (counter)
|
||||
3'd0: segv <= seg0[31:0];
|
||||
3'd1: segv <= seg0[63:32];
|
||||
3'd2: segv <= seg1[31:0];
|
||||
3'd3: segv <= seg1[63:32];
|
||||
3'd4: segv <= seg2[31:0];
|
||||
3'd5: segv <= seg2[63:32];
|
||||
3'd6: segv <= seg3[31:0];
|
||||
3'd7: segv <= seg3[63:32];
|
||||
default: segv <= 32'b0;
|
||||
endcase
|
||||
|
||||
counter <= counter + 3'd1;
|
||||
segs <= counter;
|
||||
end
|
||||
|
||||
endmodule
|
||||
Loading…
Add table
Add a link
Reference in a new issue