ParkerTenBroeck/hdl_sim
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switched away from active low, moved examples to example dir

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ParkerTenBroeck 2026-03-05 16:59:42 -05:00
parent 04c3d69cbf
commit b4841e6f40
4 changed files with 142 additions and 133 deletions
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rtl/tb.vhdl
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@ -7,7 +7,7 @@ end entity;
architecture sim of tb is
signal clk : std_logic := '0';
signal key : std_logic_vector(31 downto 0) := (others => '1'); -- active low
signal key : std_logic_vector(31 downto 0) := (others => '0');
signal sw : std_logic_vector(31 downto 0) := (others => '0');
signal led : std_logic_vector(31 downto 0) := (others => '0');