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switched away from active low, moved examples to example dir

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ParkerTenBroeck 2026-03-05 16:59:42 -05:00
parent 04c3d69cbf
commit b4841e6f40
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rtl/circuit._vhdl
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Do not modify the following entity block
entity circuit is
port (
clk: in std_logic; -- 500 Hz, period 2 ms
key: in std_logic_vector(31 downto 0); -- active low
sw: in std_logic_vector(31 downto 0); -- active high
led: out std_logic_vector(31 downto 0) := (others => '0'); -- active high
hex: out std_logic_vector(31 downto 0) := (others => '0') -- active low
);
end circuit;
architecture description of circuit is
signal counter: unsigned(31 downto 0) := x"00000000";
begin
led <= std_logic_vector(counter);
process(clk)
begin
counter <= counter+1;
end process;
end description;