mirror of
https://github.com/ParkerTenBroeck/hdl_sim.git
synced 2026-06-06 21:24:06 -04:00
switched away from active low, moved examples to example dir
This commit is contained in:
ParkerTenBroeck
parent
04c3d69cbf
commit
b4841e6f40
4 changed files with 142 additions and 133 deletions
388
examples/cpu.vhdl
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388
examples/cpu.vhdl
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic;
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key: in std_logic_vector(31 downto 0); -- active low
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sw: in std_logic_vector(31 downto 0); -- active high
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led: out std_logic_vector(31 downto 0); -- active high
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hex: out std_logic_vector(31 downto 0)
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);
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end circuit;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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Port (
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func: in unsigned(3 downto 0);
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a: in unsigned(7 downto 0);
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b: in unsigned(7 downto 0);
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carry_in: in std_logic;
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o: out unsigned(7 downto 0);
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carry_out: out std_logic;
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zero: out std_logic;
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gt: out std_logic;
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lt: out std_logic;
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eq: out std_logic
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);
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end alu;
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architecture Behavioral of alu is
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signal tmp: unsigned(8 downto 0) := "000000000";
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begin
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with func select
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tmp <= ("0"&a) + ("0"&b) when x"0",
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("0"&a) + ("0"&b) + (x"00"&carry_in) when x"1",
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("0"&a) - ("0"&b) when x"2",
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("0"&a) - ("0"&b) - (x"00"&carry_in) when x"3",
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("0"&a) and ("0"&b) when x"4",
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("0"&a) or ("0"&b) when x"5",
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("0"&a) xor ("0"&b) when x"6",
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"0"&x"00" when others;
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zero <= '1' when tmp = 0 else '0';
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eq <= '1' when a = b else '0';
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lt <= '1' when a < b else '0';
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gt <= '1' when a > b else '0';
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carry_out <= tmp(8);
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o <= tmp(7 downto 0);
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end Behavioral ; -- Behavioral
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ram_8x256 is
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Port (
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clk : in std_logic;
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we : in std_logic; -- write enable
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addr : in unsigned(7 downto 0); -- 8-bit address
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din : in unsigned(7 downto 0); -- data input
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dout : out unsigned(7 downto 0) -- data output
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);
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end ram_8x256;
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architecture Behavioral of ram_8x256 is
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type ram_type is array (0 to 255) of unsigned(7 downto 0);
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signal ram : ram_type := (others => x"AB");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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ram(to_integer(unsigned(addr))) <= din;
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end if;
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dout <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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end Behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity inst_ram_8x256 is
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Port (
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clk : in std_logic;
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addr : in unsigned(7 downto 0); -- 8-bit address
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dout : out unsigned(7 downto 0) -- data output
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);
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end inst_ram_8x256;
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architecture Behavioral of inst_ram_8x256 is
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type ram_type is array (0 to 255) of unsigned(7 downto 0);
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signal ram : ram_type := (
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0 => x"A0", -- 0 => a
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1 => x"B1", -- 1 => b
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2 => x"10", -- a+b => out
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3 => x"FE", -- out
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4 => x"AE", -- out => a
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5 => x"01", -- swap a/b
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6 => x"3F", -- cmp 144, b
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7 => x"90",
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8 => x"C7", -- jump to 2 if 144 <= b
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9 => x"02",
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10 => x"FF", -- halt
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others => (others => '0')
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);
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begin
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process(clk)
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begin
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if rising_edge(clk) or falling_edge(clk) then
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dout <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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end Behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture description of circuit is
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signal clock: std_logic;
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signal reg_pc: unsigned(7 downto 0) := "00000000";
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signal reg_a: unsigned(7 downto 0) := "00000000";
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signal reg_b: unsigned(7 downto 0) := "00000000";
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signal reg_out: unsigned(7 downto 0) := "00000000";
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signal inst_reg: unsigned(7 downto 0);
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signal inst_bus: unsigned(7 downto 0);
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signal data_read: unsigned(7 downto 0);
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signal data_write: unsigned(7 downto 0) := "00000000";
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signal data_addr: unsigned(7 downto 0) := "00000000";
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signal data_write_e: std_logic := '0';
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signal flag_carry: std_logic := '0';
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signal flag_lt: std_logic := '0';
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signal flag_gt: std_logic := '0';
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signal flag_eq: std_logic := '0';
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signal flag_zero: std_logic := '0';
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function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
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begin
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case val is
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when "0000"=> return "1000000"; --0
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when "0001"=> return "1111001"; --1
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when "0010"=> return "0100100"; --2
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when "0011"=> return "0110000"; --3
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when "0100"=> return "0011001"; --4
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when "0101"=> return "0010010"; --5
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when "0110"=> return "0000010"; --6
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when "0111"=> return "1111000"; --7
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when "1000"=> return "0000000"; --8
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when "1001"=> return "0011000"; --9
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when "1010"=> return "0001000"; --A
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when "1011"=> return "0000011"; --B
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when "1100"=> return "1000110"; --C
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when "1101"=> return "0100001"; --D
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when "1110"=> return "0000110"; --E
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when "1111"=> return "0001110"; --F
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when others=> return "1111111"; ---
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end case;
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end function;
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begin
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hex(6 downto 0) <= not dec7seg(reg_out(7 downto 4));
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hex(14 downto 8) <= not dec7seg(reg_out(3 downto 0));
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hex(22 downto 16) <= not dec7seg(reg_pc(7 downto 4));
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hex(30 downto 24) <= not dec7seg(reg_pc(3 downto 0));
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led(7 downto 0) <= std_logic_vector(reg_a);
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led(23 downto 16) <= std_logic_vector(reg_b);
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led(8) <= flag_zero;
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led(9) <= flag_eq;
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led(10) <= flag_lt;
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led(11) <= flag_gt;
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led(12) <= flag_carry;
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clock <= clk when sw(9) = '1' else key(0);
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ram_inst : entity work.inst_ram_8x256
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port map(
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clk => clk,
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addr => reg_pc,
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dout => inst_bus
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);
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ram_data : entity work.ram_8x256
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port map(
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clk => clk,
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we => data_write_e,
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addr => data_addr,
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din => data_write,
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dout => data_read
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);
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process(clock)
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variable alu_tmp: unsigned(8 downto 0) := "000000000";
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variable alu_a: unsigned(7 downto 0) := "00000000";
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variable alu_b: unsigned(7 downto 0) := "00000000";
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variable branch: std_logic := '0';
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begin
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if rising_edge(clock) then
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inst_reg <= inst_bus;
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data_write_e <= '0';
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--report "begin reg_a = " & integer'image(to_integer(unsigned(reg_a)))
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-- & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
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-- & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
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-- & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
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-- & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
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case to_integer(inst_bus) is
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-- nop
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when 16#00# => null;
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-- a, b swap
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when 16#01# =>
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reg_a <= reg_b;
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reg_b <= reg_a;
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-- alu operations a,imm
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-- alu operations imm,b
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when 16#20# to 16#3F# => reg_pc <= reg_pc+1;
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-- 0 => a
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when 16#A0# => reg_a <= x"00";
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-- 1 => a
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when 16#A1# => reg_a <= x"01";
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-- mem[reg b] => a
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when 16#AC# =>
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data_addr <= reg_b;
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-- out => a
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when 16#AE# => reg_a <= reg_out;
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-- immediate => a
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when 16#AF# => reg_pc <= reg_pc+1;
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-- 0 => b
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when 16#B0# => reg_b <= x"00";
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-- 1 => b
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when 16#B1# => reg_b <= x"01";
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-- mem[reg a] => b
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when 16#BC# =>
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data_addr <= reg_b;
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-- out => b
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when 16#BE# => reg_b <= reg_out;
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-- immediate => b
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when 16#BF# => reg_pc <= reg_pc+1;
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-- conditional jump
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when 16#C0# to 16#CF# => reg_pc <= reg_pc+1;
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-- jump imm addr abs
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when 16#D0# => reg_pc <= reg_pc+1;
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-- jump imm addr rel
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when 16#D1# => reg_pc <= reg_pc+1;
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-- jump addr reg a
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when 16#DA# => reg_pc <= reg_a-1;
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-- jump addr reg b
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when 16#DB# => reg_pc <= reg_b-1;
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-- out
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when 16#FE# => report " out = " & integer'image(to_integer(unsigned(reg_out)));
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-- halt
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when 16#FF# => reg_pc <= reg_pc-1;
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when others => null;
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end case;
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case to_integer(inst_bus(2 downto 0)) is
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when 0 => branch := flag_zero;
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when 1 => branch := flag_carry;
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when 2 => branch := flag_eq;
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when 3 => branch := not flag_eq;
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when 4 => branch := flag_lt;
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when 5 => branch := flag_gt;
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when 6 => branch := flag_lt or flag_eq;
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when 7 => branch := flag_gt or flag_eq;
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when others => null;
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end case;
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end if;
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if falling_edge(clock) then
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case to_integer(inst_reg) is
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when 16#AC# => reg_a <= data_read;
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when 16#AF# => reg_a <= inst_bus;
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when 16#BC# => reg_b <= data_read;
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when 16#BF# => reg_b <= inst_bus;
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-- alu operation a,b
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when 16#10# to 16#1F# =>
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alu_a := reg_a;
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alu_b := reg_b;
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-- alu operations a,imm
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when 16#20# to 16#2F# =>
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alu_a := reg_a;
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alu_b := inst_bus;
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-- alu operations imm,b
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when 16#30# to 16#3F# =>
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alu_a := inst_bus;
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alu_b := reg_b;
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when 16#C0# to 16#C7# => alu_tmp(7 downto 0) := inst_bus;
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when 16#C8# to 16#CF# => alu_tmp(7 downto 0) := inst_bus+reg_pc;
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when others => null;
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end case;
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-- alu operation
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if inst_reg(7 downto 4) = x"1" or inst_reg(7 downto 4) = x"2" or inst_reg(7 downto 4) = x"3" then
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with inst_reg(3 downto 0) select
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alu_tmp := ("0"&alu_a) + ("0"&alu_b) when x"0",
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("0"&alu_a) + ("0"&alu_b) + (x"00"&flag_carry) when x"1",
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("0"&alu_a) - ("0"&alu_b) when x"2",
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("0"&alu_a) - ("0"&alu_b) - (x"00"&flag_carry) when x"3",
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("0"&alu_a) and ("0"&alu_b) when x"4",
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("0"&alu_a) or ("0"&alu_b) when x"5",
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("0"&alu_a) xor ("0"&alu_b) when x"6",
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shift_left("0"&alu_a,to_integer("0"&alu_b)) when x"7",
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shift_right("0"&alu_a,to_integer("0"&alu_b)) when x"8",
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rotate_left("0"&alu_a,to_integer("0"&alu_b)) when x"9",
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rotate_right("0"&alu_a,to_integer("0"&alu_b)) when x"A",
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"0"&x"00" when others;
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flag_zero <= '1' when alu_tmp = 0 else '0';
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flag_eq <= '1' when alu_a = alu_b else '0';
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flag_lt <= '1' when alu_a < alu_b else '0';
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flag_gt <= '1' when alu_a > alu_b else '0';
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flag_carry <= alu_tmp(8);
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reg_out <= alu_tmp(7 downto 0);
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end if;
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case to_integer(inst_reg) is
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-- jump imm addr abs
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when 16#D0# => reg_pc <= inst_bus;
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-- jump imm addr rel
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when 16#D1# => reg_pc <= reg_pc+inst_bus;
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-- conditional brances
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when 16#C0# to 16#CF# =>
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if branch then
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reg_pc <= alu_tmp(7 downto 0);
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else
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reg_pc <= reg_pc+1;
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end if;
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when others => reg_pc <= reg_pc+1;
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end case;
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-- report "end reg_a = " & integer'image(to_integer(unsigned(reg_a)))
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-- & " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
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-- & " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
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-- & " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
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-- & " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
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end if;
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end process;
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end description;
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25
examples/example.vhdl
Normal file
25
examples/example.vhdl
Normal file
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@ -0,0 +1,25 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic; -- 500 Hz, period 2 ms
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key: in std_logic_vector(31 downto 0); -- active high
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sw: in std_logic_vector(31 downto 0); -- active high
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led: out std_logic_vector(31 downto 0) := (others => '0'); -- active high
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hex: out std_logic_vector(31 downto 0) := (others => '0') -- active high
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);
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end circuit;
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architecture description of circuit is
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signal counter: unsigned(31 downto 0) := x"00000000";
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begin
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led <= std_logic_vector(counter);
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process(clk)
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begin
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counter <= counter+1;
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end process;
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end description;
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