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rtl/circuit._vhdl

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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Do not modify the following entity block
+entity circuit is
+port (
+  clk: in std_logic; -- 500 Hz, period 2 ms
+  key: in std_logic_vector(3 downto 0);   -- active low
+  sw: in std_logic_vector(9 downto 0);   -- active high
+  led: out std_logic_vector(9 downto 0) := (others => '0');  -- active high
+  hex0: out std_logic_vector(6 downto 0) := (others => '0');  -- active low
+  hex1: out std_logic_vector(6 downto 0) := (others => '0')  -- active low
+  );
+end circuit;
+
+
+architecture description of circuit is
+  signal counter: unsigned(9 downto 0) := "0000000000";
+begin
+  led <= std_logic_vector(counter(9 downto 0));
+  process(clk)
+  begin
+    counter <= counter+1;
+  end process;
+end description;