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https://github.com/ParkerTenBroeck/hdl_sim.git
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ParkerTenBroeck
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26
rtl/circuit._vhdl
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26
rtl/circuit._vhdl
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic; -- 500 Hz, period 2 ms
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key: in std_logic_vector(3 downto 0); -- active low
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sw: in std_logic_vector(9 downto 0); -- active high
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led: out std_logic_vector(9 downto 0) := (others => '0'); -- active high
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hex0: out std_logic_vector(6 downto 0) := (others => '0'); -- active low
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hex1: out std_logic_vector(6 downto 0) := (others => '0') -- active low
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);
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end circuit;
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architecture description of circuit is
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signal counter: unsigned(9 downto 0) := "0000000000";
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begin
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led <= std_logic_vector(counter(9 downto 0));
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process(clk)
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begin
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counter <= counter+1;
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end process;
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end description;
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329
rtl/circuit.vhdl
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329
rtl/circuit.vhdl
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Do not modify the following entity block
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entity circuit is
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port (
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clk: in std_logic;
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key: in std_logic_vector(31 downto 0); -- active low
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sw: in std_logic_vector(31 downto 0); -- active high
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led: out std_logic_vector(31 downto 0); -- active high
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hex: out std_logic_vector(31 downto 0) -- active low
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);
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end circuit;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity alu is
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Port (
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func: in unsigned(3 downto 0);
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a: in unsigned(7 downto 0);
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b: in unsigned(7 downto 0);
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carry_in: in std_logic;
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o: out unsigned(7 downto 0);
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carry_out: out std_logic;
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zero: out std_logic;
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gt: out std_logic;
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lt: out std_logic;
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eq: out std_logic
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);
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end alu;
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architecture Behavioral of alu is
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signal tmp: unsigned(8 downto 0);
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begin
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with func select
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tmp <= ("0"&a) + ("0"&b) when x"0",
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("0"&a) + ("0"&b) + (x"00"&carry_in) when x"1",
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("0"&a) - ("0"&b) when x"2",
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("0"&a) - ("0"&b) - (x"00"&carry_in) when x"3",
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("0"&a) and ("0"&b) when x"4",
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("0"&a) or ("0"&b) when x"5",
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("0"&a) xor ("0"&b) when x"6",
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"0"&x"00" when others;
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zero <= '1' when tmp = 0 else '0';
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eq <= '1' when a = b else '0';
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lt <= '1' when a < b else '0';
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gt <= '1' when a > b else '0';
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carry_out <= tmp(8);
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o <= tmp(7 downto 0);
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end Behavioral ; -- Behavioral
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ram_8x256 is
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Port (
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clk : in std_logic;
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we : in std_logic; -- write enable
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addr : in unsigned(7 downto 0); -- 8-bit address
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din : in unsigned(7 downto 0); -- data input
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dout : out unsigned(7 downto 0) -- data output
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);
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end ram_8x256;
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architecture Behavioral of ram_8x256 is
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type ram_type is array (0 to 255) of unsigned(7 downto 0);
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signal ram : ram_type := (others => x"AB");
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if we = '1' then
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ram(to_integer(unsigned(addr))) <= din;
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end if;
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dout <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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end Behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity inst_ram_8x256 is
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Port (
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clk : in std_logic;
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addr : in unsigned(7 downto 0); -- 8-bit address
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dout : out unsigned(7 downto 0) -- data output
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);
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end inst_ram_8x256;
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architecture Behavioral of inst_ram_8x256 is
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type ram_type is array (0 to 255) of unsigned(7 downto 0);
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signal ram : ram_type := (
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0 => x"A0", -- 0 => a
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2 => x"B1", -- 1 => b
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3 => x"10", -- a+b => out
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4 => x"AE", -- out => a
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5 => x"10", -- a+b => out
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6 => x"BE", -- out => b
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7 => x"D0", -- jump to 3
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8 => x"03",
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others => (others => '0')
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);
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begin
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process(clk)
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begin
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if rising_edge(clk) or falling_edge(clk) then
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dout <= ram(to_integer(unsigned(addr)));
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end if;
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end process;
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end Behavioral;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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architecture description of circuit is
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signal clock: std_logic;
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signal reg_pc: unsigned(7 downto 0) := "00000000";
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signal reg_a: unsigned(7 downto 0) := "00000000";
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signal reg_b: unsigned(7 downto 0) := "00000000";
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signal reg_out: unsigned(7 downto 0) := "00000000";
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signal inst_reg: unsigned(7 downto 0);
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signal inst_bus: unsigned(7 downto 0);
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signal data_read: unsigned(7 downto 0);
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signal data_write: unsigned(7 downto 0);
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signal data_addr: unsigned(7 downto 0) := "00000000";
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signal data_write_e: std_logic := '0';
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signal flag_carry: std_logic := '0';
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signal flag_lt: std_logic := '0';
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signal flag_gt: std_logic := '0';
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signal flag_eq: std_logic := '0';
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signal flag_zero: std_logic := '0';
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signal alu_a, alu_b, alu_o : unsigned(7 downto 0);
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signal alu_func : unsigned(3 downto 0);
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signal alu_carry, alu_zero, alu_gt, alu_lt, alu_eq : std_logic;
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function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
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begin
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case val is
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when "0000"=> return "1000000"; --0
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when "0001"=> return "1111001"; --1
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when "0010"=> return "0100100"; --2
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when "0011"=> return "0110000"; --3
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when "0100"=> return "0011001"; --4
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when "0101"=> return "0010010"; --5
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when "0110"=> return "0000010"; --6
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when "0111"=> return "1111000"; --7
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when "1000"=> return "0000000"; --8
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when "1001"=> return "0011000"; --9
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when "1010"=> return "0001000"; --A
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when "1011"=> return "0000011"; --B
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when "1100"=> return "1000110"; --C
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when "1101"=> return "0100001"; --D
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when "1110"=> return "0000110"; --E
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when "1111"=> return "0001110"; --F
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when others=> return "1111111"; ---
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end case;
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end function;
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begin
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-- hex(7 downto 4) <= dec7seg(reg_out(7 downto 4));
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-- hex(3 downto 0) <= dec7seg(reg_out(3 downto 0));
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clock <= clk when sw(9) = '1' else sw(8);
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ram_inst : entity work.inst_ram_8x256
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port map(
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clk => clk,
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addr => reg_pc,
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dout => inst_bus
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);
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ram_data : entity work.ram_8x256
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port map(
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clk => clk,
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we => data_write_e,
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addr => data_addr,
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din => data_write,
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dout => data_read
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);
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alu : entity work.alu
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port map(
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func => alu_func,
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a => alu_a,
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b => alu_b,
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carry_in => flag_carry,
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o => alu_o,
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carry_out => alu_carry,
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zero => alu_zero,
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gt => alu_gt,
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lt => alu_lt,
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eq => alu_eq
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);
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process(clock)
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variable out_extended : unsigned(8 downto 0);
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begin
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if rising_edge(clock) then
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inst_reg <= inst_bus;
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data_write_e <= '0';
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report "begin reg_a = " & integer'image(to_integer(unsigned(reg_a)))
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& " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
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& " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
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& " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
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& " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
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-- alu operations a,b
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if inst_reg(7 downto 4) = x"1" then
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alu_func <= inst_reg(3 downto 0);
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alu_a <= reg_a;
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alu_b <= reg_b;
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reg_out <= alu_o;
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end if;
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-- alu operations a,imm
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if inst_reg(7 downto 4) = x"2" then
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alu_func <= inst_reg(3 downto 0);
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alu_a <= reg_a;
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reg_pc <= reg_pc+1;
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end if;
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-- alu operations imm,b
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if inst_reg(7 downto 4) = x"3" then
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alu_func <= inst_reg(3 downto 0);
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alu_b <= reg_b;
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reg_pc <= reg_pc+1;
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end if;
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case inst_bus is
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-- nop
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when x"00" => null;
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-- 0 => a
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when x"A0" => reg_a <= x"00";
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-- 1 => a
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when x"A1" => reg_a <= x"01";
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-- mem[reg b] => a
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when x"AC" =>
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data_addr <= reg_b;
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-- out => a
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when x"AE" => reg_a <= reg_out;
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-- immediate => a
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when x"AF" => reg_pc <= reg_pc+1;
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-- 0 => b
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when x"B0" => reg_b <= x"00";
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-- 1 => b
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when x"B1" => reg_b <= x"01";
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-- mem[reg a] => b
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when x"BC" =>
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data_addr <= reg_b;
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-- out => b
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when x"BE" => reg_b <= reg_out;
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-- immediate => b
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when x"BF" => reg_pc <= reg_pc+1;
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-- conditional
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-- jump imm addr abs
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when x"D0" => reg_pc <= reg_pc+1;
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-- jump imm addr rel
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when x"D1" => reg_pc <= reg_pc+1;
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-- jump addr reg a
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when x"DA" => reg_pc <= reg_a-1;
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-- jump addr reg b
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when x"DB" => reg_pc <= reg_b-1;
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-- halt
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when x"FF" => reg_pc <= reg_pc-1;
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when others => null;
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end case;
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end if;
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if falling_edge(clock) then
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case inst_reg is
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when x"AC" => reg_a <= data_read;
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when x"AF" => reg_a <= inst_bus;
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when x"BC" => reg_b <= data_read;
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when x"BF" => reg_b <= inst_bus;
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when others => null;
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end case;
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case inst_reg is
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-- jump imm addr abs
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when x"D0" => reg_pc <= inst_bus;
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-- jump imm addr rel
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when x"D1" => reg_pc <= reg_pc+inst_bus;
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when others => reg_pc <= reg_pc+1;
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end case;
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report "end reg_a = " & integer'image(to_integer(unsigned(reg_a)))
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& " reg_b = " & integer'image(to_integer(unsigned(reg_b)))
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& " reg_out = " & integer'image(to_integer(unsigned(reg_out)))
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& " reg_pc = " & integer'image(to_integer(unsigned(reg_pc)))
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& " inst_bus = " & integer'image(to_integer(unsigned(inst_bus)));
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end if;
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end process;
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end description;
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94
rtl/tb.vhdl
Normal file
94
rtl/tb.vhdl
Normal file
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@ -0,0 +1,94 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity tb is
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end entity;
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architecture sim of tb is
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signal clk : std_logic := '0';
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signal key : std_logic_vector(31 downto 0) := (others => '1'); -- active low
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signal sw : std_logic_vector(31 downto 0) := (others => '0');
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signal led : std_logic_vector(31 downto 0) := (others => '0');
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signal hex : std_logic_vector(31 downto 0) := (others => '0');
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-- Foreign subprograms MUST be declared in the declarative region (here),
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-- and MUST have a body (even dummy) to satisfy VHDL.
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procedure ffi_init is
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begin
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end procedure;
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attribute foreign of ffi_init : procedure is
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"VHPIDIRECT ffi_init";
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function ffi_get_sw return integer is
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begin
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return 0;
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end function;
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attribute foreign of ffi_get_sw : function is
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"VHPIDIRECT ffi_get_sw";
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function ffi_get_key return integer is
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begin
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return 0;
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end function;
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attribute foreign of ffi_get_key : function is "VHPIDIRECT ffi_get_key";
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procedure ffi_set_outputs(led_i : integer; hex_i : integer) is
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begin
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end procedure;
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attribute foreign of ffi_set_outputs : procedure is
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"VHPIDIRECT ffi_set_outputs";
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function clean_slv(v : std_logic_vector) return std_logic_vector is
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variable r : std_logic_vector(v'range);
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begin
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for i in v'range loop
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if v(i) = '1' then
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r(i) := '1';
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else
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r(i) := '0';
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end if;
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end loop;
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return r;
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end function;
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begin
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dut: entity work.circuit
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port map (
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clk => clk,
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key => key,
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sw => sw,
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led => led,
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hex => hex
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);
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-- 500 Hz clock (2 ms period)
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clk <= not clk after 1 ms;
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process
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variable sw_i : integer;
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variable key_i : integer;
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begin
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ffi_init; -- starts Rust listener thread
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wait for 0 ns;
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while true loop
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wait until rising_edge(clk) or falling_edge(clk);
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sw_i := ffi_get_sw;
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key_i := ffi_get_key;
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sw <= std_logic_vector(to_unsigned(sw_i, 32));
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key <= std_logic_vector(to_unsigned(key_i, 32));
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ffi_set_outputs(
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to_integer(unsigned(clean_slv(led))),
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to_integer(unsigned(clean_slv(hex)))
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);
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end loop;
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end process;
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|
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end architecture;
|
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