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updated segment interface

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Parker TenBroeck 2026-03-12 21:49:21 -04:00
parent 4773ab5e9e
commit 5746846896
9 changed files with 183 additions and 195 deletions
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14
src/cpu.vhdl
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@ -9,10 +9,8 @@ port (
btn: in std_logic_vector(31 downto 0);
sw: in std_logic_vector(31 downto 0);
led: out std_logic_vector(31 downto 0);
seg0: out std_logic_vector(31 downto 0);
seg1: out std_logic_vector(31 downto 0);
seg2: out std_logic_vector(31 downto 0);
seg3: out std_logic_vector(31 downto 0)
segv: out std_logic_vector(31 downto 0);
segs: out std_logic_vector(31 downto 0)
);
end circuit;
@ -71,11 +69,11 @@ architecture description of circuit is
begin
seg0(6 downto 0) <= dec7seg(reg_out(7 downto 4));
seg0(14 downto 8) <= dec7seg(reg_out(3 downto 0));
segs(6 downto 0) <= dec7seg(reg_out(7 downto 4));
segs(14 downto 8) <= dec7seg(reg_out(3 downto 0));
seg0(22 downto 16) <= dec7seg(reg_pc(7 downto 4));
seg0(30 downto 24) <= dec7seg(reg_pc(3 downto 0));
segs(22 downto 16) <= dec7seg(reg_pc(7 downto 4));
segs(30 downto 24) <= dec7seg(reg_pc(3 downto 0));
led(7 downto 0) <= std_logic_vector(reg_a);
led(23 downto 16) <= std_logic_vector(reg_b);