From 4773ab5e9ec98db2f5036a695dd7ba9fa47cdbbd Mon Sep 17 00:00:00 2001
From: Parker TenBroeck <51721964+ParkerTenBroeck@users.noreply.github.com>
Date: Thu, 12 Mar 2026 12:31:59 -0400
Subject: [PATCH] sinage issue

---
 rtl/tb.vhdl | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/rtl/tb.vhdl b/rtl/tb.vhdl
index 7be37eb..f072a81 100644
--- a/rtl/tb.vhdl
+++ b/rtl/tb.vhdl
@@ -90,11 +90,11 @@ begin
       btn <= std_logic_vector(to_signed(btn_i, 32));
 
       ffi_set_outputs(
-          to_integer(unsigned(clean_slv(led))),
-          to_integer(unsigned(clean_slv(seg0))),
-          to_integer(unsigned(clean_slv(seg1))),
-          to_integer(unsigned(clean_slv(seg2))),
-          to_integer(unsigned(clean_slv(seg3)))
+          to_integer(signed(clean_slv(led))),
+          to_integer(signed(clean_slv(seg0))),
+          to_integer(signed(clean_slv(seg1))),
+          to_integer(signed(clean_slv(seg2))),
+          to_integer(signed(clean_slv(seg3)))
       );
     end loop;
   end process;