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ParkerTenBroeck 2026-03-09 15:53:06 -04:00
parent e6c5947949
commit 191101591e
1 changed files with 21 additions and 21 deletions
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examples/cpu.vhdl
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@ -161,34 +161,34 @@ architecture description of circuit is
function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
begin begin
case val is case val is
when "0000"=> return "1000000"; --0 when "0000"=> return "0111111"; --0
when "0001"=> return "1111001"; --1 when "0001"=> return "0000110"; --1
when "0010"=> return "0100100"; --2 when "0010"=> return "1011011"; --2
when "0011"=> return "0110000"; --3 when "0011"=> return "1001111"; --3
when "0100"=> return "0011001"; --4 when "0100"=> return "1100110"; --4
when "0101"=> return "0010010"; --5 when "0101"=> return "1101101"; --5
when "0110"=> return "0000010"; --6 when "0110"=> return "1111101"; --6
when "0111"=> return "1111000"; --7 when "0111"=> return "0000111"; --7
when "1000"=> return "0000000"; --8 when "1000"=> return "1111111"; --8
when "1001"=> return "0011000"; --9 when "1001"=> return "1100111"; --9
when "1010"=> return "0001000"; --A when "1010"=> return "1110111"; --A
when "1011"=> return "0000011"; --B when "1011"=> return "1111100"; --B
when "1100"=> return "1000110"; --C when "1100"=> return "0111001"; --C
when "1101"=> return "0100001"; --D when "1101"=> return "1011110"; --D
when "1110"=> return "0000110"; --E when "1110"=> return "1111001"; --E
when "1111"=> return "0001110"; --F when "1111"=> return "1110001"; --F
when others=> return "1111111"; --- when others=> return "0000000"; ---
end case; end case;
end function; end function;
begin begin
seg0(6 downto 0) <= not dec7seg(reg_out(7 downto 4)); seg0(6 downto 0) <= dec7seg(reg_out(7 downto 4));
seg0(14 downto 8) <= not dec7seg(reg_out(3 downto 0)); seg0(14 downto 8) <= dec7seg(reg_out(3 downto 0));
seg0(22 downto 16) <= not dec7seg(reg_pc(7 downto 4)); seg0(22 downto 16) <= dec7seg(reg_pc(7 downto 4));
seg0(30 downto 24) <= not dec7seg(reg_pc(3 downto 0)); seg0(30 downto 24) <= dec7seg(reg_pc(3 downto 0));
led(7 downto 0) <= std_logic_vector(reg_a); led(7 downto 0) <= std_logic_vector(reg_a);
led(23 downto 16) <= std_logic_vector(reg_b); led(23 downto 16) <= std_logic_vector(reg_b);