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1 changed files with 21 additions and 21 deletions
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@ -161,34 +161,34 @@ architecture description of circuit is
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function dec7seg(val: unsigned(3 downto 0)) return std_logic_vector is
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begin
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case val is
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when "0000"=> return "1000000"; --0
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when "0001"=> return "1111001"; --1
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when "0010"=> return "0100100"; --2
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when "0011"=> return "0110000"; --3
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when "0100"=> return "0011001"; --4
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when "0101"=> return "0010010"; --5
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when "0110"=> return "0000010"; --6
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when "0111"=> return "1111000"; --7
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when "1000"=> return "0000000"; --8
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when "1001"=> return "0011000"; --9
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when "1010"=> return "0001000"; --A
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when "1011"=> return "0000011"; --B
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when "1100"=> return "1000110"; --C
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when "1101"=> return "0100001"; --D
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when "1110"=> return "0000110"; --E
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when "1111"=> return "0001110"; --F
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when others=> return "1111111"; ---
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when "0000"=> return "0111111"; --0
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when "0001"=> return "0000110"; --1
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when "0010"=> return "1011011"; --2
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when "0011"=> return "1001111"; --3
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when "0100"=> return "1100110"; --4
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when "0101"=> return "1101101"; --5
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when "0110"=> return "1111101"; --6
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when "0111"=> return "0000111"; --7
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when "1000"=> return "1111111"; --8
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when "1001"=> return "1100111"; --9
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when "1010"=> return "1110111"; --A
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when "1011"=> return "1111100"; --B
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when "1100"=> return "0111001"; --C
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when "1101"=> return "1011110"; --D
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when "1110"=> return "1111001"; --E
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when "1111"=> return "1110001"; --F
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when others=> return "0000000"; ---
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end case;
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end function;
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begin
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seg0(6 downto 0) <= not dec7seg(reg_out(7 downto 4));
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seg0(14 downto 8) <= not dec7seg(reg_out(3 downto 0));
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seg0(6 downto 0) <= dec7seg(reg_out(7 downto 4));
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seg0(14 downto 8) <= dec7seg(reg_out(3 downto 0));
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seg0(22 downto 16) <= not dec7seg(reg_pc(7 downto 4));
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seg0(30 downto 24) <= not dec7seg(reg_pc(3 downto 0));
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seg0(22 downto 16) <= dec7seg(reg_pc(7 downto 4));
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seg0(30 downto 24) <= dec7seg(reg_pc(3 downto 0));
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led(7 downto 0) <= std_logic_vector(reg_a);
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led(23 downto 16) <= std_logic_vector(reg_b);
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